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PCI: Mask writes to RO bits in the status reg of PCI config space
authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 18 Dec 2008 22:43:33 +0000 (22:43 +0000)
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 18 Dec 2008 22:43:33 +0000 (22:43 +0000)
commit8098ed414ada4265f646e94d65eca063b3689f50
tree4bcb312026eee379d04427b54edae8a42289f186tree | snapshot
parent2231ef1084f1522508880e99ba60647f8d312c74commit | diff
PCI: Mask writes to RO bits in the status reg of PCI config space

The Status register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.

Signed-off-by: Amit Shah <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6091 c046a42c-6fe2-441c-8c8c-71466251a162
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