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target-arm: Implement XScale cache lockdown operations as NOPs
authorPeter Maydell <[email protected]>
Thu, 1 May 2014 14:24:44 +0000 (15:24 +0100)
committerPeter Maydell <[email protected]>
Thu, 1 May 2014 14:24:44 +0000 (15:24 +0100)
commit3b7715796401ad1b00f752217fe8f425915e801b
treee45b953a40a49d6ddea723481bd7acef9a66d2d6tree | snapshot
parent051b9980b99dbfba22ea5f79bd3708d513ae121dcommit | diff
target-arm: Implement XScale cache lockdown operations as NOPs

XScale defines some implementation-specific coprocessor registers
for doing cache lockdown operations. Since QEMU doesn't model a
cache no proper implementation is possible, but NOP out the
registers so that guest code like u-boot that tries to use them
doesn't crash.

Reported-by: <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
target-arm/helper.c diff | blob | blame | history
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