target/riscv: Support mcycle/minstret write operation

target/riscv: Support mcycle/minstret write operation

mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.

Support mcycle/minstret through generic counter infrastructure.

Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-Id: <20220620231603.2547260[email protected]>
Signed-off-by: Alistair Francis <[email protected]>