Git Repo - qemu.git/commit - target-xtensa/translate.c

]> Git Repo - qemu.git/commit - target-xtensa/translate.c

author	Max Filippov <[email protected]>
	Sun, 15 Jan 2012 01:40:50 +0000 (05:40 +0400)
committer	Max Filippov <[email protected]>
	Sat, 18 Feb 2012 10:55:52 +0000 (14:55 +0400)
commit	35b5c0442798c1754f1d56452528dce5fee003c2
tree	ffc45877d83c476a726558b1a0121521ea3de40a	tree \| snapshot
parent	e61dc8f72c096e084106d5e97101d9d88f642d0e	commit \| diff

target-xtensa: add ICOUNT SR and debug exception

ICOUNT SR gets incremented on every instruction completion provided that
CINTLEVEL at the beginning of the instruction execution is lower than
ICOUNTLEVEL.

When ICOUNT would increment to 0 a debug exception is raised if
CINTLEVEL is lower than DEBUGLEVEL.

See ISA, 4.7.7.5 for more details.

Signed-off-by: Max Filippov <[email protected]>

target-xtensa/cpu.h		diff \| blob \| blame \| history
target-xtensa/translate.c		diff \| blob \| blame \| history

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