]> Git Repo - qemu.git/commit
x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
authorCathy Zhang <[email protected]>
Mon, 13 Apr 2020 06:52:38 +0000 (14:52 +0800)
committerPaolo Bonzini <[email protected]>
Wed, 10 Jun 2020 16:10:27 +0000 (12:10 -0400)
commit353f98c9ad52ff4b8cfe553c90be04f747a14c98
tree9bba0c487797641b43e752af185eb3925489d61b
parentc781a2cc423155079acf45e5ce79e6635f109fc4
x86/cpu: Enable AVX512_VP2INTERSECT cpu feature

AVX512_VP2INTERSECT compute vector pair intersection to a pair
of mask registers, which is introduced with intel Tiger Lake,
defining as CPUID.(EAX=7,ECX=0):EDX[bit 08].

Refer to the following release spec:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Cathy Zhang <[email protected]>
Message-Id: <1586760758[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
target/i386/cpu.c
target/i386/cpu.h
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