]> Git Repo - qemu.git/commit - target/riscv/csr.c
target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
authorRichard Henderson <[email protected]>
Mon, 23 Aug 2021 19:55:21 +0000 (12:55 -0700)
committerAlistair Francis <[email protected]>
Wed, 1 Sep 2021 01:59:12 +0000 (11:59 +1000)
commit33979526cad412b72afd1989a22dcd218b2ce170
tree6a806a15bc58da0f051ed0e65ad4ccb42e4ad447
parent6ecf39e2dd854ff7ea21c365165c1957061263bb
target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation

We distinguish write-only by passing ret_value as NULL.

Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210823195529[email protected]
Signed-off-by: Alistair Francis <[email protected]>
target/riscv/csr.c
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