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target/arm: Improve masking of SCR RES0 bits
authorRichard Henderson <[email protected]>
Fri, 26 Jun 2020 03:31:00 +0000 (20:31 -0700)
committerPeter Maydell <[email protected]>
Fri, 26 Jun 2020 13:31:11 +0000 (14:31 +0100)
commit252e8c69669599b4bcff802df300726300292f47
tree0ba5ce6e95dc426838678822db3c46640d5f0a9etree | snapshot
parentc7fd0baac0c24defec66263799faa8618327b352commit | diff
target/arm: Improve masking of SCR RES0 bits

Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: 20200626033144[email protected]
Signed-off-by: Peter Maydell <[email protected]>
target/arm/helper.c diff | blob | blame | history
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