]> Git Repo - qemu.git/commit
target/riscv: Fix implementation of HLVX.WU instruction
authorGeorg Kotheimer <[email protected]>
Tue, 13 Oct 2020 17:22:23 +0000 (19:22 +0200)
committerAlistair Francis <[email protected]>
Thu, 22 Oct 2020 19:00:22 +0000 (12:00 -0700)
commit1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa
tree10470a252045e34f111eacae67b8d12095138024
parent4aeb9e26c219a85f465eb2cc7ef6939a3c71944f
target/riscv: Fix implementation of HLVX.WU instruction

The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.

Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions")
Signed-off-by: Georg Kotheimer <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20201013172223[email protected]
Signed-off-by: Alistair Francis <[email protected]>
target/riscv/op_helper.c
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