Git Repo - qemu.git/commit - target/riscv/csr.c

]> Git Repo - qemu.git/commit - target/riscv/csr.c

author	Alistair Francis <[email protected]>
	Tue, 5 May 2020 20:04:50 +0000 (13:04 -0700)
committer	Alistair Francis <[email protected]>
	Wed, 3 Jun 2020 16:11:51 +0000 (09:11 -0700)
commit	1a9540d1f1a9c5022d9273d0244e5809679dd33b
tree	9ea2807a5edfdafaeef072edff21da9ba8ee8493	tree \| snapshot
parent	65a117da6ec5f0226952368d544cfb5c2a1dcead	commit \| diff

target/riscv: Drop support for ISA spec version 1.09.1

The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>

docs/system/deprecated.rst		diff \| blob \| blame \| history
target/riscv/cpu.c		diff \| blob \| blame \| history
target/riscv/cpu.h		diff \| blob \| blame \| history
target/riscv/cpu_helper.c		diff \| blob \| blame \| history
target/riscv/csr.c		diff \| blob \| blame \| history
target/riscv/insn_trans/trans_privileged.inc.c		diff \| blob \| blame \| history
target/riscv/monitor.c		diff \| blob \| blame \| history
target/riscv/op_helper.c		diff \| blob \| blame \| history

Empty description

RSS Atom

This page took 0.027058 seconds and 4 git commands to generate.