Git Repo - qemu.git/commit - target/sparc/translate.c

]> Git Repo - qemu.git/commit - target/sparc/translate.c

author	Tony Nguyen <[email protected]>
	Fri, 23 Aug 2019 18:10:58 +0000 (04:10 +1000)
committer	Richard Henderson <[email protected]>
	Tue, 3 Sep 2019 15:30:38 +0000 (08:30 -0700)
commit	14776ab5a12972ea439c7fb2203a4c15a09094b4
tree	b53091625b410a722bf5f4e17a9631457994eed4	tree \| snapshot
parent	fec105c2abda8567ec15230429c41429b5ee307c	commit \| diff

tcg: TCGMemOp is now accelerator independent MemOp

Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Signed-off-by: Tony Nguyen <[email protected]>
Acked-by: David Gibson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Acked-by: Cornelia Huck <[email protected]>
Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906 [email protected]>
Signed-off-by: Richard Henderson <[email protected]>

39 files changed:

MAINTAINERS		diff \| blob \| blame \| history
accel/tcg/cputlb.c		diff \| blob \| blame \| history
include/exec/memop.h	[new file with mode: 0644]	blob
target/alpha/translate.c		diff \| blob \| blame \| history
target/arm/translate-a64.c		diff \| blob \| blame \| history
target/arm/translate-a64.h		diff \| blob \| blame \| history
target/arm/translate-sve.c		diff \| blob \| blame \| history
target/arm/translate.c		diff \| blob \| blame \| history
target/arm/translate.h		diff \| blob \| blame \| history
target/hppa/translate.c		diff \| blob \| blame \| history
target/i386/translate.c		diff \| blob \| blame \| history
target/m68k/translate.c		diff \| blob \| blame \| history
target/microblaze/translate.c		diff \| blob \| blame \| history
target/mips/translate.c		diff \| blob \| blame \| history
target/openrisc/translate.c		diff \| blob \| blame \| history
target/ppc/translate.c		diff \| blob \| blame \| history
target/riscv/insn_trans/trans_rva.inc.c		diff \| blob \| blame \| history
target/riscv/insn_trans/trans_rvi.inc.c		diff \| blob \| blame \| history
target/s390x/translate.c		diff \| blob \| blame \| history
target/s390x/translate_vx.inc.c		diff \| blob \| blame \| history
target/sparc/translate.c		diff \| blob \| blame \| history
target/tilegx/translate.c		diff \| blob \| blame \| history
target/tricore/translate.c		diff \| blob \| blame \| history
tcg/README		diff \| blob \| blame \| history
tcg/aarch64/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/arm/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/i386/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/mips/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/optimize.c		diff \| blob \| blame \| history
tcg/ppc/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/riscv/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/s390/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/sparc/tcg-target.inc.c		diff \| blob \| blame \| history
tcg/tcg-op.c		diff \| blob \| blame \| history
tcg/tcg-op.h		diff \| blob \| blame \| history
tcg/tcg.c		diff \| blob \| blame \| history
tcg/tcg.h		diff \| blob \| blame \| history
trace/mem-internal.h		diff \| blob \| blame \| history
trace/mem.h		diff \| blob \| blame \| history

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