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target/riscv: More accurate handling of `sip` CSR
authorJonathan Behrens <[email protected]>
Tue, 7 May 2019 22:36:46 +0000 (18:36 -0400)
committerPalmer Dabbelt <[email protected]>
Fri, 24 May 2019 19:09:25 +0000 (12:09 -0700)
commit087b051a51a0c2a5bc1e8d435a484a8896b4176b
tree1601ee3643102d79f17f561e2a18e3be81f191e3tree | snapshot
parent4cc16b3b9282e04fab8e84d136540757e82af019commit | diff
target/riscv: More accurate handling of `sip` CSR

According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.

Signed-off-by: Jonathan Behrens <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
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