Git Repo - qemu.git/commit

]> Git Repo - qemu.git/commit

author	Bin Meng <[email protected]>
	Tue, 26 Jan 2021 06:00:01 +0000 (14:00 +0800)
committer	Alistair Francis <[email protected]>
	Thu, 4 Mar 2021 14:43:29 +0000 (09:43 -0500)
commit	0694dabe9763847f3010b54ab3ec7d367d2f0ff0
tree	a92f68117045ffa9455a2529bd5fe09e52791249	tree \| snapshot
parent	62d1076678a4c3d2385cc492283061b710bb0a60	commit \| diff

hw/ssi: Add SiFive SPI controller support

This adds the SiFive SPI controller model for the FU540 SoC.
The direct memory-mapped SPI flash mode is unsupported.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210126060007 [email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/ssi/Kconfig		diff \| blob \| blame \| history
hw/ssi/meson.build		diff \| blob \| blame \| history
hw/ssi/sifive_spi.c	[new file with mode: 0644]	blob
include/hw/ssi/sifive_spi.h	[new file with mode: 0644]	blob

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