X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/ef397e88e96d4a798bd190bcd0c43865c3725ae2..b6cd0ea1205dd4623ccfe796ee6c1a4da3141d99:/hw/ppc405_uc.c diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index efbc399d2d..b6b25b7ca8 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -21,8 +21,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "vl.h" +#include "hw.h" +#include "ppc.h" #include "ppc405.h" +#include "pc.h" +#include "qemu-timer.h" +#include "sysemu.h" extern int loglevel; extern FILE *logfile; @@ -36,7 +40,7 @@ extern FILE *logfile; #define DEBUG_GPT #define DEBUG_MAL #define DEBUG_CLOCKS -//#define DEBUG_UNASSIGNED +//#define DEBUG_CLOCKS_LL ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, uint32_t flags) @@ -294,7 +298,7 @@ static void opba_writeb (void *opaque, ppc4xx_opba_t *opba; #ifdef DEBUG_OPBA - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif opba = opaque; switch (addr - opba->base) { @@ -326,7 +330,7 @@ static void opba_writew (void *opaque, target_phys_addr_t addr, uint32_t value) { #ifdef DEBUG_OPBA - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif opba_writeb(opaque, addr, value >> 8); opba_writeb(opaque, addr + 1, value); @@ -349,7 +353,7 @@ static void opba_writel (void *opaque, target_phys_addr_t addr, uint32_t value) { #ifdef DEBUG_OPBA - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif opba_writeb(opaque, addr, value >> 24); opba_writeb(opaque, addr + 1, value >> 16); @@ -385,7 +389,7 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, if (opba != NULL) { opba->base = offset; #ifdef DEBUG_OPBA - printf("%s: offset=" PADDRX "\n", __func__, offset); + printf("%s: offset " PADDRX "\n", __func__, offset); #endif ppc4xx_mmio_register(env, mmio, offset, 0x002, opba_read, opba_write, opba); @@ -425,6 +429,10 @@ enum { SDRAM0_CFGDATA = 0x011, }; +/* XXX: TOFIX: some patches have made this code become inconsistent: + * there are type inconsistencies, mixing target_phys_addr_t, target_ulong + * and uint32_t + */ static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size) { @@ -453,8 +461,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base, bcr = 0x000C0000; break; default: - printf("%s: invalid RAM size " TARGET_FMT_plx "\n", - __func__, ram_size); + printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size); return 0x00000000; } bcr |= ram_base & 0xFF800000; @@ -487,7 +494,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) if (*bcrp & 0x00000001) { /* Unmap RAM */ #ifdef DEBUG_SDRAM - printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", + printf("%s: unmap RAM area " PADDRX " " ADDRX "\n", __func__, sdram_base(*bcrp), sdram_size(*bcrp)); #endif cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), @@ -496,7 +503,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) *bcrp = bcr & 0xFFDEE001; if (enabled && (bcr & 0x00000001)) { #ifdef DEBUG_SDRAM - printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", + printf("%s: Map RAM area " PADDRX " " ADDRX "\n", __func__, sdram_base(bcr), sdram_size(bcr)); #endif cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), @@ -525,7 +532,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) for (i = 0; i < sdram->nbanks; i++) { #ifdef DEBUG_SDRAM - printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", + printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n", __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); #endif cpu_register_physical_memory(sdram_base(sdram->bcr[i]), @@ -1106,7 +1113,7 @@ static void ppc405_gpio_writeb (void *opaque, gpio = opaque; #ifdef DEBUG_GPIO - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif } @@ -1129,7 +1136,7 @@ static void ppc405_gpio_writew (void *opaque, gpio = opaque; #ifdef DEBUG_GPIO - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif } @@ -1152,7 +1159,7 @@ static void ppc405_gpio_writel (void *opaque, gpio = opaque; #ifdef DEBUG_GPIO - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif } @@ -1186,7 +1193,7 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, ppc405_gpio_reset(gpio); qemu_register_reset(&ppc405_gpio_reset, gpio); #ifdef DEBUG_GPIO - printf("%s: offset=" PADDRX "\n", __func__, offset); + printf("%s: offset " PADDRX "\n", __func__, offset); #endif ppc4xx_mmio_register(env, mmio, offset, 0x038, ppc405_gpio_read, ppc405_gpio_write, gpio); @@ -1214,9 +1221,9 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio, void *serial; #ifdef DEBUG_SERIAL - printf("%s: offset=" PADDRX "\n", __func__, offset); + printf("%s: offset " PADDRX "\n", __func__, offset); #endif - serial = serial_mm_init(offset, 0, irq, chr, 0); + serial = serial_mm_init(offset, 0, irq, 399193, chr, 0); ppc4xx_mmio_register(env, mmio, offset, 0x008, serial_mm_read, serial_mm_write, serial); } @@ -1244,7 +1251,9 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, uint32_t dsarc, uint32_t dsacntl) { #ifdef DEBUG_OCM - printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n", + printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 + " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 + " (%08" PRIx32 " %08" PRIx32 ")\n", isarc, isacntl, dsarc, dsacntl, ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); #endif @@ -1252,14 +1261,14 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { if (ocm->isacntl & 0x80000000) { /* Unmap previously assigned memory region */ - printf("OCM unmap ISA %08x\n", ocm->isarc); + printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); cpu_register_physical_memory(ocm->isarc, 0x04000000, IO_MEM_UNASSIGNED); } if (isacntl & 0x80000000) { /* Map new instruction memory region */ #ifdef DEBUG_OCM - printf("OCM map ISA %08x\n", isarc); + printf("OCM map ISA %08" PRIx32 "\n", isarc); #endif cpu_register_physical_memory(isarc, 0x04000000, ocm->offset | IO_MEM_RAM); @@ -1272,7 +1281,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { /* Unmap previously assigned memory region */ #ifdef DEBUG_OCM - printf("OCM unmap DSA %08x\n", ocm->dsarc); + printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); #endif cpu_register_physical_memory(ocm->dsarc, 0x04000000, IO_MEM_UNASSIGNED); @@ -1283,7 +1292,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, if (!(isacntl & 0x80000000) || dsarc != isarc) { /* Map new data memory region */ #ifdef DEBUG_OCM - printf("OCM map DSA %08x\n", dsarc); + printf("OCM map DSA %08" PRIx32 "\n", dsarc); #endif cpu_register_physical_memory(dsarc, 0x04000000, ocm->offset | IO_MEM_RAM); @@ -1471,7 +1480,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) break; } #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret); + printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret); #endif return ret; @@ -1483,7 +1492,7 @@ static void ppc4xx_i2c_writeb (void *opaque, ppc4xx_i2c_t *i2c; #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif i2c = opaque; switch (addr - i2c->base) { @@ -1553,7 +1562,7 @@ static void ppc4xx_i2c_writew (void *opaque, target_phys_addr_t addr, uint32_t value) { #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif ppc4xx_i2c_writeb(opaque, addr, value >> 8); ppc4xx_i2c_writeb(opaque, addr + 1, value); @@ -1578,7 +1587,7 @@ static void ppc4xx_i2c_writel (void *opaque, target_phys_addr_t addr, uint32_t value) { #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif ppc4xx_i2c_writeb(opaque, addr, value >> 24); ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); @@ -1625,7 +1634,7 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, i2c->irq = irq; ppc4xx_i2c_reset(i2c); #ifdef DEBUG_I2C - printf("%s: offset=" PADDRX "\n", __func__, offset); + printf("%s: offset " PADDRX "\n", __func__, offset); #endif ppc4xx_mmio_register(env, mmio, offset, 0x011, i2c_read, i2c_write, i2c); @@ -1664,7 +1673,7 @@ static void ppc4xx_gpt_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) { #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif /* XXX: generate a bus fault */ } @@ -1682,7 +1691,7 @@ static void ppc4xx_gpt_writew (void *opaque, target_phys_addr_t addr, uint32_t value) { #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif /* XXX: generate a bus fault */ } @@ -1801,7 +1810,7 @@ static void ppc4xx_gpt_writel (void *opaque, int idx; #ifdef DEBUG_I2C - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); #endif gpt = opaque; switch (addr - gpt->base) { @@ -1909,7 +1918,7 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio, gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); ppc4xx_gpt_reset(gpt); #ifdef DEBUG_GPT - printf("%s: offset=" PADDRX "\n", __func__, offset); + printf("%s: offset " PADDRX "\n", __func__, offset); #endif ppc4xx_mmio_register(env, mmio, offset, 0x0D4, gpt_read, gpt_write, gpt); @@ -2578,13 +2587,13 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], ppc405_dma_init(env, dma_irqs); /* Serial ports */ if (serial_hds[0] != NULL) { - ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); + ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); } if (serial_hds[1] != NULL) { - ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); + ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); } /* IIC controller */ - ppc405_i2c_init(env, mmio, 0x500, pic[29]); + ppc405_i2c_init(env, mmio, 0x500, pic[2]); /* GPIO */ ppc405_gpio_init(env, mmio, 0x700); /* CPU control */ @@ -2652,9 +2661,13 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) VCO_out = 0; if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ - // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); +#ifdef DEBUG_CLOCKS_LL + printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); +#endif D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ - // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); +#ifdef DEBUG_CLOCKS_LL + printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); +#endif VCO_out = cpc->sysclk * M * D; if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { /* Error - unlock the PLL */ @@ -2679,53 +2692,53 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) } /* Now, compute all other clocks */ D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ -#ifdef DEBUG_CLOCKS - // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); +#ifdef DEBUG_CLOCKS_LL + printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); #endif CPU_clk = PLL_out / D; D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ -#ifdef DEBUG_CLOCKS - // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); +#ifdef DEBUG_CLOCKS_LL + printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); #endif PLB_clk = CPU_clk / D; D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ -#ifdef DEBUG_CLOCKS - // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); +#ifdef DEBUG_CLOCKS_LL + printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); #endif OPB_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ -#ifdef DEBUG_CLOCKS - // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); +#ifdef DEBUG_CLOCKS_LL + printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); #endif EBC_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ -#ifdef DEBUG_CLOCKS - // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); +#ifdef DEBUG_CLOCKS_LL + printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); #endif MAL_clk = PLB_clk / D; D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ -#ifdef DEBUG_CLOCKS - // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D); +#ifdef DEBUG_CLOCKS_LL + printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); #endif PCI_clk = PLB_clk / D; D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ -#ifdef DEBUG_CLOCKS - // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D); +#ifdef DEBUG_CLOCKS_LL + printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); #endif UART0_clk = PLL_out / D; D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ -#ifdef DEBUG_CLOCKS - // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D); +#ifdef DEBUG_CLOCKS_LL + printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); #endif UART1_clk = PLL_out / D; #ifdef DEBUG_CLOCKS - printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64 + printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); - printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n", + printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 + " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 + " UART1 %" PRIu32 "\n", CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, UART0_clk, UART1_clk); - printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb, - cpc->clk_setup[PPC405EP_CPU_CLK].opaque); #endif /* Setup CPU clocks */ clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); @@ -2917,49 +2930,50 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ - ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init); + /* XXX 405EP has no ECC interrupt */ + ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); offset = 0; for (i = 0; i < 2; i++) offset += ram_sizes[i]; /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ - dma_irqs[0] = pic[26]; - dma_irqs[1] = pic[25]; - dma_irqs[2] = pic[24]; - dma_irqs[3] = pic[23]; + dma_irqs[0] = pic[5]; + dma_irqs[1] = pic[6]; + dma_irqs[2] = pic[7]; + dma_irqs[3] = pic[8]; ppc405_dma_init(env, dma_irqs); /* IIC controller */ - ppc405_i2c_init(env, mmio, 0x500, pic[29]); + ppc405_i2c_init(env, mmio, 0x500, pic[2]); /* GPIO */ ppc405_gpio_init(env, mmio, 0x700); /* Serial ports */ if (serial_hds[0] != NULL) { - ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); + ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]); } if (serial_hds[1] != NULL) { - ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); + ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); } /* OCM */ ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); offset += 4096; /* GPT */ - gpt_irqs[0] = pic[12]; - gpt_irqs[1] = pic[11]; - gpt_irqs[2] = pic[10]; - gpt_irqs[3] = pic[9]; - gpt_irqs[4] = pic[8]; + gpt_irqs[0] = pic[19]; + gpt_irqs[1] = pic[20]; + gpt_irqs[2] = pic[21]; + gpt_irqs[3] = pic[22]; + gpt_irqs[4] = pic[23]; ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs); /* PCI */ - /* Uses pic[28], pic[15], pic[13] */ + /* Uses pic[3], pic[16], pic[18] */ /* MAL */ - mal_irqs[0] = pic[20]; - mal_irqs[1] = pic[19]; - mal_irqs[2] = pic[18]; - mal_irqs[3] = pic[17]; + mal_irqs[0] = pic[11]; + mal_irqs[1] = pic[12]; + mal_irqs[2] = pic[13]; + mal_irqs[3] = pic[14]; ppc405_mal_init(env, mal_irqs); /* Ethernet */ - /* Uses pic[22], pic[16], pic[14] */ + /* Uses pic[9], pic[15], pic[17] */ /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); *offsetp = offset;