X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/e43941318d22795df91682fec6720540ede6ad02..b2bf03a90ca3024213e354d3e0a6bc0cc8fc31e8:/hw/ppc405_boards.c diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 735adc95e3..9abede7e05 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -31,6 +31,7 @@ #include "boards.h" #include "qemu-log.h" #include "loader.h" +#include "blockdev.h" #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2048 * 1024) @@ -163,7 +164,8 @@ static void ref405ep_fpga_init (uint32_t base) fpga = qemu_mallocz(sizeof(ref405ep_fpga_t)); fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, - ref405ep_fpga_write, fpga); + ref405ep_fpga_write, fpga, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00000100, fpga_memory); qemu_register_reset(&ref405ep_fpga_reset, fpga); } @@ -181,17 +183,18 @@ static void ref405ep_init (ram_addr_t ram_size, qemu_irq *pic; ram_addr_t sram_offset, bios_offset, bdloc; target_phys_addr_t ram_bases[2], ram_sizes[2]; - target_ulong sram_size, bios_size; + target_ulong sram_size; + long bios_size; //int phy_addr = 0; //static int phy_addr = 1; - target_ulong kernel_base, kernel_size, initrd_base, initrd_size; + target_ulong kernel_base, initrd_base; + long kernel_size, initrd_size; int linux_boot; int fl_idx, fl_sectors, len; - int ppc_boot_device = boot_device[0]; DriveInfo *dinfo; /* XXX: fix this */ - ram_bases[0] = qemu_ram_alloc(0x08000000); + ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000); ram_sizes[0] = 0x08000000; ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; @@ -203,7 +206,7 @@ static void ref405ep_init (ram_addr_t ram_size, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * 1024; - sram_offset = qemu_ram_alloc(sram_size); + sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); #ifdef DEBUG_BOARD_INIT printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset); #endif @@ -218,17 +221,18 @@ static void ref405ep_init (ram_addr_t ram_size, dinfo = drive_get(IF_PFLASH, 0, fl_idx); if (dinfo) { bios_size = bdrv_getlength(dinfo->bdrv); - bios_offset = qemu_ram_alloc(bios_size); + bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size); fl_sectors = (bios_size + 65535) >> 16; #ifdef DEBUG_BOARD_INIT - printf("Register parallel flash %d size " TARGET_FMT_lx - " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n", + printf("Register parallel flash %d size %lx" + " at offset %08lx addr %lx '%s' %d\n", fl_idx, bios_size, bios_offset, -bios_size, bdrv_get_device_name(dinfo->bdrv), fl_sectors); #endif pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, dinfo->bdrv, 65536, fl_sectors, 1, - 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, + 1); fl_idx++; } else #endif @@ -236,7 +240,7 @@ static void ref405ep_init (ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("Load BIOS from file\n"); #endif - bios_offset = qemu_ram_alloc(BIOS_SIZE); + bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = BIOS_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); @@ -307,7 +311,7 @@ static void ref405ep_init (ram_addr_t ram_size, kernel_filename); exit(1); } - printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx, + printf("Load kernel size %ld at " TARGET_FMT_lx, kernel_size, kernel_base); /* load initrd */ if (initrd_filename) { @@ -325,7 +329,6 @@ static void ref405ep_init (ram_addr_t ram_size, } env->gpr[4] = initrd_base; env->gpr[5] = initrd_size; - ppc_boot_device = 'm'; if (kernel_cmdline != NULL) { len = strlen(kernel_cmdline); bdloc -= ((len + 255) & ~255); @@ -486,7 +489,8 @@ static void taihu_cpld_init (uint32_t base) cpld = qemu_mallocz(sizeof(taihu_cpld_t)); cpld_memory = cpu_register_io_memory(taihu_cpld_read, - taihu_cpld_write, cpld); + taihu_cpld_write, cpld, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00000100, cpld_memory); qemu_register_reset(&taihu_cpld_reset, cpld); } @@ -499,28 +503,27 @@ static void taihu_405ep_init(ram_addr_t ram_size, const char *cpu_model) { char *filename; - CPUPPCState *env; qemu_irq *pic; ram_addr_t bios_offset; target_phys_addr_t ram_bases[2], ram_sizes[2]; - target_ulong bios_size; - target_ulong kernel_base, kernel_size, initrd_base, initrd_size; + long bios_size; + target_ulong kernel_base, initrd_base; + long kernel_size, initrd_size; int linux_boot; int fl_idx, fl_sectors; - int ppc_boot_device = boot_device[0]; DriveInfo *dinfo; /* RAM is soldered to the board so the size cannot be changed */ - ram_bases[0] = qemu_ram_alloc(0x04000000); + ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000); ram_sizes[0] = 0x04000000; - ram_bases[1] = qemu_ram_alloc(0x04000000); + ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000); ram_sizes[1] = 0x04000000; ram_size = 0x08000000; #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, - kernel_filename == NULL ? 0 : 1); + ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, + kernel_filename == NULL ? 0 : 1); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT printf("%s: register BIOS\n", __func__); @@ -533,16 +536,17 @@ static void taihu_405ep_init(ram_addr_t ram_size, /* XXX: should check that size is 2MB */ // bios_size = 2 * 1024 * 1024; fl_sectors = (bios_size + 65535) >> 16; - bios_offset = qemu_ram_alloc(bios_size); + bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size); #ifdef DEBUG_BOARD_INIT - printf("Register parallel flash %d size " TARGET_FMT_lx - " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n", + printf("Register parallel flash %d size %lx" + " at offset %08lx addr %lx '%s' %d\n", fl_idx, bios_size, bios_offset, -bios_size, bdrv_get_device_name(dinfo->bdrv), fl_sectors); #endif pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, dinfo->bdrv, 65536, fl_sectors, 1, - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, + 1); fl_idx++; } else #endif @@ -552,7 +556,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, #endif if (bios_name == NULL) bios_name = BIOS_FILENAME; - bios_offset = qemu_ram_alloc(BIOS_SIZE); + bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset)); @@ -576,15 +580,16 @@ static void taihu_405ep_init(ram_addr_t ram_size, bios_size = 32 * 1024 * 1024; fl_sectors = (bios_size + 65535) >> 16; #ifdef DEBUG_BOARD_INIT - printf("Register parallel flash %d size " TARGET_FMT_lx + printf("Register parallel flash %d size %lx" " at offset %08lx addr " TARGET_FMT_lx " '%s'\n", fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000, bdrv_get_device_name(dinfo->bdrv)); #endif - bios_offset = qemu_ram_alloc(bios_size); + bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size); pflash_cfi02_register(0xfc000000, bios_offset, dinfo->bdrv, 65536, fl_sectors, 1, - 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, + 1); fl_idx++; } /* Register CLPD & LCD display */ @@ -622,7 +627,6 @@ static void taihu_405ep_init(ram_addr_t ram_size, initrd_base = 0; initrd_size = 0; } - ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0;