X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/ca87d03b77aade91926972b7e20b5382b59d1c77..511b13e2c9b426b3c56060909693de5097f0b496:/hw/etraxfs_timer.c

diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
index 7c9eb920c7..9076a49884 100644
--- a/hw/etraxfs_timer.c
+++ b/hw/etraxfs_timer.c
@@ -21,10 +21,10 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include <stdio.h>
-#include <sys/time.h>
-#include "hw.h"
+#include "sysbus.h"
+#include "sysemu.h"
 #include "qemu-timer.h"
+#include "ptimer.h"
 
 #define D(x)
 
@@ -36,239 +36,316 @@
 #define RW_TMR1_CTRL  0x18
 #define R_TIME        0x38
 #define RW_WD_CTRL    0x40
+#define R_WD_STAT     0x44
 #define RW_INTR_MASK  0x48
 #define RW_ACK_INTR   0x4c
 #define R_INTR        0x50
 #define R_MASKED_INTR 0x54
 
-struct fs_timer_t {
-	CPUState *env;
-	qemu_irq *irq;
-	target_phys_addr_t base;
-
-	QEMUBH *bh;
-	ptimer_state *ptimer;
-	unsigned int limit;
-	int scale;
-	uint32_t mask;
-	struct timeval last;
-
-	uint32_t rw_intr_mask;
-	uint32_t rw_ack_intr;
-	uint32_t r_intr;
+struct etrax_timer {
+    SysBusDevice busdev;
+    MemoryRegion mmio;
+    qemu_irq irq;
+    qemu_irq nmi;
+
+    QEMUBH *bh_t0;
+    QEMUBH *bh_t1;
+    QEMUBH *bh_wd;
+    ptimer_state *ptimer_t0;
+    ptimer_state *ptimer_t1;
+    ptimer_state *ptimer_wd;
+
+    int wd_hits;
+
+    /* Control registers.  */
+    uint32_t rw_tmr0_div;
+    uint32_t r_tmr0_data;
+    uint32_t rw_tmr0_ctrl;
+
+    uint32_t rw_tmr1_div;
+    uint32_t r_tmr1_data;
+    uint32_t rw_tmr1_ctrl;
+
+    uint32_t rw_wd_ctrl;
+
+    uint32_t rw_intr_mask;
+    uint32_t rw_ack_intr;
+    uint32_t r_intr;
+    uint32_t r_masked_intr;
 };
 
-/* diff two timevals.  Return a single int in us. */
-int diff_timeval_us(struct timeval *a, struct timeval *b)
+static uint64_t
+timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
 {
-        int diff;
+    struct etrax_timer *t = opaque;
+    uint32_t r = 0;
 
-        /* assume these values are signed.  */
-        diff = (a->tv_sec - b->tv_sec) * 1000 * 1000;
-        diff += (a->tv_usec - b->tv_usec);
-        return diff;
+    switch (addr) {
+    case R_TMR0_DATA:
+        r = ptimer_get_count(t->ptimer_t0);
+        break;
+    case R_TMR1_DATA:
+        r = ptimer_get_count(t->ptimer_t1);
+        break;
+    case R_TIME:
+        r = qemu_get_clock_ns(vm_clock) / 10;
+        break;
+    case RW_INTR_MASK:
+        r = t->rw_intr_mask;
+        break;
+    case R_MASKED_INTR:
+        r = t->r_intr & t->rw_intr_mask;
+        break;
+    default:
+        D(printf ("%s %x\n", __func__, addr));
+        break;
+    }
+    return r;
 }
 
-static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
+static void update_ctrl(struct etrax_timer *t, int tnum)
 {
-	struct fs_timer_t *t = opaque;
-	CPUState *env = t->env;
-	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", 
-		  addr, env->pc);
-	return 0;
+    unsigned int op;
+    unsigned int freq;
+    unsigned int freq_hz;
+    unsigned int div;
+    uint32_t ctrl;
+
+    ptimer_state *timer;
+
+    if (tnum == 0) {
+        ctrl = t->rw_tmr0_ctrl;
+        div = t->rw_tmr0_div;
+        timer = t->ptimer_t0;
+    } else {
+        ctrl = t->rw_tmr1_ctrl;
+        div = t->rw_tmr1_div;
+        timer = t->ptimer_t1;
+    }
+
+
+    op = ctrl & 3;
+    freq = ctrl >> 2;
+    freq_hz = 32000000;
+
+    switch (freq)
+    {
+    case 0:
+    case 1:
+        D(printf ("extern or disabled timer clock?\n"));
+        break;
+    case 4: freq_hz =  29493000; break;
+    case 5: freq_hz =  32000000; break;
+    case 6: freq_hz =  32768000; break;
+    case 7: freq_hz = 100000000; break;
+    default:
+        abort();
+        break;
+    }
+
+    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
+    ptimer_set_freq(timer, freq_hz);
+    ptimer_set_limit(timer, div, 0);
+
+    switch (op)
+    {
+        case 0:
+            /* Load.  */
+            ptimer_set_limit(timer, div, 1);
+            break;
+        case 1:
+            /* Hold.  */
+            ptimer_stop(timer);
+            break;
+        case 2:
+            /* Run.  */
+            ptimer_run(timer, 0);
+            break;
+        default:
+            abort();
+            break;
+    }
 }
 
-static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
+static void timer_update_irq(struct etrax_timer *t)
 {
-	struct fs_timer_t *t = opaque;
-	D(CPUState *env = t->env);
-	uint32_t r = 0;
-
-	/* Make addr relative to this instances base.  */
-	addr -= t->base;
-	switch (addr) {
-	case R_TMR0_DATA:
-		break;
-	case R_TMR1_DATA:
-		D(printf ("R_TMR1_DATA\n"));
-		break;
-	case R_TIME:
-	{
-		struct timeval now;
-		gettimeofday(&now, NULL);
-		if (!(t->last.tv_sec == 0 
-		      && t->last.tv_usec == 0)) {
-			r = diff_timeval_us(&now, &t->last);
-			r *= 1000; /* convert to ns.  */
-			r++; /* make sure we increase for each call.  */
-		}
-		t->last = now;
-		break;
-	}
-
-	case RW_INTR_MASK:
-		r = t->rw_intr_mask;
-		break;
-	case R_MASKED_INTR:
-		r = t->r_intr & t->rw_intr_mask;
-		break;
-	default:
-		D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
-		break;
-	}
-	return r;
+    t->r_intr &= ~(t->rw_ack_intr);
+    t->r_masked_intr = t->r_intr & t->rw_intr_mask;
+
+    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
+    qemu_set_irq(t->irq, !!t->r_masked_intr);
 }
 
-static void
-timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void timer0_hit(void *opaque)
 {
-	struct fs_timer_t *t = opaque;
-	CPUState *env = t->env;
-	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", 
-		  addr, env->pc);
+    struct etrax_timer *t = opaque;
+    t->r_intr |= 1;
+    timer_update_irq(t);
 }
 
-static void write_ctrl(struct fs_timer_t *t, uint32_t v)
+static void timer1_hit(void *opaque)
 {
-	int op;
-	int freq;
-	int freq_hz;
-
-	op = v & 3;
-	freq = v >> 2;
-	freq_hz = 32000000;
-
-	switch (freq)
-	{
-	case 0:
-	case 1:
-		D(printf ("extern or disabled timer clock?\n"));
-		break;
-	case 4: freq_hz =  29493000; break;
-	case 5: freq_hz =  32000000; break;
-	case 6: freq_hz =  32768000; break;
-	case 7: freq_hz = 100000000; break;
-	default:
-		abort();
-		break;
-	}
-
-	D(printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit));
-	t->scale = 0;
-	if (t->limit > 2048)
-	{
-		t->scale = 2048;
-		ptimer_set_period(t->ptimer, freq_hz / t->scale);
-	}
-
-	switch (op)
-	{
-		case 0:
-			D(printf ("limit=%d %d\n", 
-				  t->limit, t->limit/t->scale));
-			ptimer_set_limit(t->ptimer, t->limit / t->scale, 1);
-			break;
-		case 1:
-			ptimer_stop(t->ptimer);
-			break;
-		case 2:
-			ptimer_run(t->ptimer, 0);
-			break;
-		default:
-			abort();
-			break;
-	}
+    struct etrax_timer *t = opaque;
+    t->r_intr |= 2;
+    timer_update_irq(t);
 }
 
-static void timer_ack_irq(struct fs_timer_t *t)
+static void watchdog_hit(void *opaque)
 {
-	if (!(t->r_intr & t->mask & t->rw_intr_mask))
-		qemu_irq_lower(t->irq[0]);
+    struct etrax_timer *t = opaque;
+    if (t->wd_hits == 0) {
+        /* real hw gives a single tick before reseting but we are
+           a bit friendlier to compensate for our slower execution.  */
+        ptimer_set_count(t->ptimer_wd, 10);
+        ptimer_run(t->ptimer_wd, 1);
+        qemu_irq_raise(t->nmi);
+    }
+    else
+        qemu_system_reset_request();
+
+    t->wd_hits++;
+}
+
+static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
+{
+    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
+    unsigned int wd_key = t->rw_wd_ctrl >> 9;
+    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
+    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
+    unsigned int new_cmd = (value >> 8) & 1;
+
+    /* If the watchdog is enabled, they written key must match the
+       complement of the previous.  */
+    wd_key = ~wd_key & ((1 << 7) - 1);
+
+    if (wd_en && wd_key != new_key)
+        return;
+
+    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
+         wd_en, new_key, wd_key, new_cmd, wd_cnt));
+
+    if (t->wd_hits)
+        qemu_irq_lower(t->nmi);
+
+    t->wd_hits = 0;
+
+    ptimer_set_freq(t->ptimer_wd, 760);
+    if (wd_cnt == 0)
+        wd_cnt = 256;
+    ptimer_set_count(t->ptimer_wd, wd_cnt);
+    if (new_cmd)
+        ptimer_run(t->ptimer_wd, 1);
+    else
+        ptimer_stop(t->ptimer_wd);
+
+    t->rw_wd_ctrl = value;
 }
 
 static void
-timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+timer_write(void *opaque, target_phys_addr_t addr,
+            uint64_t val64, unsigned int size)
 {
-	struct fs_timer_t *t = opaque;
-	CPUState *env = t->env;
-
-	D(printf ("%s %x %x pc=%x\n",
-		__func__, addr, value, env->pc));
-	/* Make addr relative to this instances base.  */
-	addr -= t->base;
-	switch (addr)
-	{
-		case RW_TMR0_DIV:
-			D(printf ("RW_TMR0_DIV=%x\n", value));
-			t->limit = value;
-			break;
-		case RW_TMR0_CTRL:
-			D(printf ("RW_TMR0_CTRL=%x\n", value));
-			write_ctrl(t, value);
-			break;
-		case RW_TMR1_DIV:
-			D(printf ("RW_TMR1_DIV=%x\n", value));
-			break;
-		case RW_TMR1_CTRL:
-			D(printf ("RW_TMR1_CTRL=%x\n", value));
-			break;
-		case RW_INTR_MASK:
-			D(printf ("RW_INTR_MASK=%x\n", value));
-			t->rw_intr_mask = value;
-			break;
-		case RW_WD_CTRL:
-			D(printf ("RW_WD_CTRL=%x\n", value));
-			break;
-		case RW_ACK_INTR:
-			t->r_intr &= ~value;
-			timer_ack_irq(t);
-			break;
-		default:
-			printf ("%s %x %x pc=%x\n",
-				__func__, addr, value, env->pc);
-			break;
-	}
+    struct etrax_timer *t = opaque;
+    uint32_t value = val64;
+
+    switch (addr)
+    {
+        case RW_TMR0_DIV:
+            t->rw_tmr0_div = value;
+            break;
+        case RW_TMR0_CTRL:
+            D(printf ("RW_TMR0_CTRL=%x\n", value));
+            t->rw_tmr0_ctrl = value;
+            update_ctrl(t, 0);
+            break;
+        case RW_TMR1_DIV:
+            t->rw_tmr1_div = value;
+            break;
+        case RW_TMR1_CTRL:
+            D(printf ("RW_TMR1_CTRL=%x\n", value));
+            t->rw_tmr1_ctrl = value;
+            update_ctrl(t, 1);
+            break;
+        case RW_INTR_MASK:
+            D(printf ("RW_INTR_MASK=%x\n", value));
+            t->rw_intr_mask = value;
+            timer_update_irq(t);
+            break;
+        case RW_WD_CTRL:
+            timer_watchdog_update(t, value);
+            break;
+        case RW_ACK_INTR:
+            t->rw_ack_intr = value;
+            timer_update_irq(t);
+            t->rw_ack_intr = 0;
+            break;
+        default:
+            printf ("%s " TARGET_FMT_plx " %x\n",
+                __func__, addr, value);
+            break;
+    }
 }
 
-static CPUReadMemoryFunc *timer_read[] = {
-    &timer_rinvalid,
-    &timer_rinvalid,
-    &timer_readl,
+static const MemoryRegionOps timer_ops = {
+    .read = timer_read,
+    .write = timer_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4
+    }
 };
 
-static CPUWriteMemoryFunc *timer_write[] = {
-    &timer_winvalid,
-    &timer_winvalid,
-    &timer_writel,
-};
+static void etraxfs_timer_reset(void *opaque)
+{
+    struct etrax_timer *t = opaque;
+
+    ptimer_stop(t->ptimer_t0);
+    ptimer_stop(t->ptimer_t1);
+    ptimer_stop(t->ptimer_wd);
+    t->rw_wd_ctrl = 0;
+    t->r_intr = 0;
+    t->rw_intr_mask = 0;
+    qemu_irq_lower(t->irq);
+}
 
-static void timer_irq(void *opaque)
+static int etraxfs_timer_init(SysBusDevice *dev)
 {
-	struct fs_timer_t *t = opaque;
-	t->r_intr |= t->mask;
-	if (t->mask & t->rw_intr_mask) {
-		D(printf("%s raise\n", __func__));
-		qemu_irq_raise(t->irq[0]);
-	}
+    struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
+
+    t->bh_t0 = qemu_bh_new(timer0_hit, t);
+    t->bh_t1 = qemu_bh_new(timer1_hit, t);
+    t->bh_wd = qemu_bh_new(watchdog_hit, t);
+    t->ptimer_t0 = ptimer_init(t->bh_t0);
+    t->ptimer_t1 = ptimer_init(t->bh_t1);
+    t->ptimer_wd = ptimer_init(t->bh_wd);
+
+    sysbus_init_irq(dev, &t->irq);
+    sysbus_init_irq(dev, &t->nmi);
+
+    memory_region_init_io(&t->mmio, &timer_ops, t, "etraxfs-timer", 0x5c);
+    sysbus_init_mmio(dev, &t->mmio);
+    qemu_register_reset(etraxfs_timer_reset, t);
+    return 0;
+}
+
+static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
+{
+    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+    sdc->init = etraxfs_timer_init;
 }
 
-void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, 
-			target_phys_addr_t base)
+static TypeInfo etraxfs_timer_info = {
+    .name          = "etraxfs,timer",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof (struct etrax_timer),
+    .class_init    = etraxfs_timer_class_init,
+};
+
+static void etraxfs_timer_register_types(void)
 {
-	static struct fs_timer_t *t;
-	int timer_regs;
-
-	t = qemu_mallocz(sizeof *t);
-	if (!t)
-		return;
-
-	t->bh = qemu_bh_new(timer_irq, t);
-	t->ptimer = ptimer_init(t->bh);
-	t->irq = irqs + 26;
-	t->mask = 1;
-	t->env = env;
-	t->base = base;
-
-	timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
-	cpu_register_physical_memory (base, 0x5c, timer_regs);
+    type_register_static(&etraxfs_timer_info);
 }
+
+type_init(etraxfs_timer_register_types)