X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/c227f0995e1722a1abccc28cadf0664266bd8043..558c86345a8bacd8c763a9184baa169362fe3a43:/hw/sh7750.c

diff --git a/hw/sh7750.c b/hw/sh7750.c
index 933bbc0c7a..0291d5fd49 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -206,7 +206,7 @@ static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
     switch (addr) {
     default:
 	error_access("byte read", addr);
-	assert(0);
+        abort();
     }
 }
 
@@ -240,7 +240,7 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
 	return 0;
     default:
 	error_access("word read", addr);
-	assert(0);
+        abort();
     }
 }
 
@@ -287,7 +287,7 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
 	return s->cpu->prr;
     default:
 	error_access("long read", addr);
-	assert(0);
+        abort();
     }
 }
 
@@ -303,7 +303,7 @@ static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
     }
 
     error_access("byte write", addr);
-    assert(0);
+    abort();
 }
 
 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@@ -349,12 +349,12 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
 	s->gpioic = mem_value;
 	if (mem_value != 0) {
 	    fprintf(stderr, "I/O interrupts not implemented\n");
-	    assert(0);
+            abort();
 	}
 	return;
     default:
 	error_access("word write", addr);
-	assert(0);
+        abort();
     }
 }
 
@@ -396,8 +396,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
 	portb_changed(s, temp);
 	return;
     case SH7750_MMUCR_A7:
-	s->cpu->mmucr = mem_value;
-	return;
+        if (mem_value & MMUCR_TI) {
+            cpu_sh4_invalidate_tlb(s->cpu);
+        }
+        s->cpu->mmucr = mem_value & ~MMUCR_TI;
+        return;
     case SH7750_PTEH_A7:
         /* If asid changes, clear all registered tlb entries. */
 	if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
@@ -430,7 +433,7 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
 	return;
     default:
 	error_access("long write", addr);
-	assert(0);
+        abort();
     }
 }
 
@@ -615,7 +618,7 @@ static struct intc_group groups_irl[] = {
 
 static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
 {
-    assert(0);
+    abort();
 
     return 0;
 }
@@ -632,7 +635,7 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
     case MM_ITLB_ADDR:
     case MM_ITLB_DATA:
         /* XXXXX */
-        assert(0);
+        abort();
 	break;
     case MM_OCACHE_ADDR:
     case MM_OCACHE_DATA:
@@ -641,10 +644,10 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
     case MM_UTLB_ADDR:
     case MM_UTLB_DATA:
         /* XXXXX */
-        assert(0);
+        abort();
 	break;
     default:
-        assert(0);
+        abort();
     }
 
     return ret;
@@ -653,7 +656,7 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
 static void invalid_write(void *opaque, target_phys_addr_t addr,
 			  uint32_t mem_value)
 {
-    assert(0);
+    abort();
 }
 
 static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
@@ -669,7 +672,7 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
     case MM_ITLB_ADDR:
     case MM_ITLB_DATA:
         /* XXXXX */
-        assert(0);
+        abort();
 	break;
     case MM_OCACHE_ADDR:
     case MM_OCACHE_DATA:
@@ -680,10 +683,10 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
 	break;
     case MM_UTLB_DATA:
         /* XXXXX */
-        assert(0);
+        abort();
 	break;
     default:
-        assert(0);
+        abort();
 	break;
     }
 }