X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/c190ea07290c3973f4549d6e2ed9e8b2cddaf497..ec17457588ad944794502cfe1c76a34ff8a11618:/hw/apb_pci.c diff --git a/hw/apb_pci.c b/hw/apb_pci.c index f222f3c0eb..c232946280 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -26,148 +26,209 @@ Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is the secondary PCI bridge. */ -#include "hw.h" +#include "sysbus.h" #include "pci.h" +#include "pci_host.h" +#include "pci_bridge.h" +#include "pci_internals.h" +#include "apb_pci.h" +#include "sysemu.h" +#include "exec-memory.h" /* debug APB */ //#define DEBUG_APB #ifdef DEBUG_APB -#define APB_DPRINTF(fmt, args...) \ -do { printf("APB: " fmt , ##args); } while (0) +#define APB_DPRINTF(fmt, ...) \ +do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #else -#define APB_DPRINTF(fmt, args...) +#define APB_DPRINTF(fmt, ...) #endif -typedef target_phys_addr_t pci_addr_t; -#include "pci_host.h" - -typedef PCIHostState APBState; - -static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - APBState *s = opaque; +/* + * Chipset docs: + * PBM: "UltraSPARC IIi User's Manual", + * http://www.sun.com/processors/manuals/805-0087.pdf + * + * APB: "Advanced PCI Bridge (APB) User's Manual", + * http://www.sun.com/processors/manuals/805-1251.pdf + */ -#ifdef TARGET_WORDS_BIGENDIAN - val = bswap32(val); -#endif - APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, - val); - s->config_reg = val; -} +#define PBM_PCI_IMR_MASK 0x7fffffff +#define PBM_PCI_IMR_ENABLED 0x80000000 + +#define POR (1 << 31) +#define SOFT_POR (1 << 30) +#define SOFT_XIR (1 << 29) +#define BTN_POR (1 << 28) +#define BTN_XIR (1 << 27) +#define RESET_MASK 0xf8000000 +#define RESET_WCMASK 0x98000000 +#define RESET_WMASK 0x60000000 + +typedef struct APBState { + SysBusDevice busdev; + PCIBus *bus; + MemoryRegion apb_config; + MemoryRegion pci_config; + MemoryRegion pci_mmio; + MemoryRegion pci_ioport; + uint32_t iommu[4]; + uint32_t pci_control[16]; + uint32_t pci_irq_map[8]; + uint32_t obio_irq_map[32]; + qemu_irq pci_irqs[32]; + uint32_t reset_control; + unsigned int nr_resets; +} APBState; -static uint32_t pci_apb_config_readl (void *opaque, - target_phys_addr_t addr) +static void apb_config_writel (void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { APBState *s = opaque; - uint32_t val; - - val = s->config_reg; -#ifdef TARGET_WORDS_BIGENDIAN - val = bswap32(val); -#endif - APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, - val); - return val; -} - -static CPUWriteMemoryFunc *pci_apb_config_write[] = { - &pci_apb_config_writel, - &pci_apb_config_writel, - &pci_apb_config_writel, -}; -static CPUReadMemoryFunc *pci_apb_config_read[] = { - &pci_apb_config_readl, - &pci_apb_config_readl, - &pci_apb_config_readl, -}; + APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val); -static void apb_config_writel (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - //PCIBus *s = opaque; - - switch (addr & 0x3f) { - case 0x00: // Control/Status - case 0x10: // AFSR - case 0x18: // AFAR - case 0x20: // Diagnostic - case 0x28: // Target address space - // XXX + switch (addr & 0xffff) { + case 0x30 ... 0x4f: /* DMA error registers */ + /* XXX: not implemented yet */ + break; + case 0x200 ... 0x20b: /* IOMMU */ + s->iommu[(addr & 0xf) >> 2] = val; + break; + case 0x20c ... 0x3ff: /* IOMMU flush */ + break; + case 0xc00 ... 0xc3f: /* PCI interrupt control */ + if (addr & 4) { + s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK; + s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK; + } + break; + case 0x2000 ... 0x202f: /* PCI control */ + s->pci_control[(addr & 0x3f) >> 2] = val; + break; + case 0xf020 ... 0xf027: /* Reset control */ + if (addr & 4) { + val &= RESET_MASK; + s->reset_control &= ~(val & RESET_WCMASK); + s->reset_control |= val & RESET_WMASK; + if (val & SOFT_POR) { + s->nr_resets = 0; + qemu_system_reset_request(); + } else if (val & SOFT_XIR) { + qemu_system_reset_request(); + } + } + break; + case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ + case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ + case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ + case 0xf000 ... 0xf01f: /* FFB config, memory control */ + /* we don't care */ default: break; } } -static uint32_t apb_config_readl (void *opaque, - target_phys_addr_t addr) +static uint64_t apb_config_readl (void *opaque, + target_phys_addr_t addr, unsigned size) { - //PCIBus *s = opaque; + APBState *s = opaque; uint32_t val; - switch (addr & 0x3f) { - case 0x00: // Control/Status - case 0x10: // AFSR - case 0x18: // AFAR - case 0x20: // Diagnostic - case 0x28: // Target address space - // XXX + switch (addr & 0xffff) { + case 0x30 ... 0x4f: /* DMA error registers */ + val = 0; + /* XXX: not implemented yet */ + break; + case 0x200 ... 0x20b: /* IOMMU */ + val = s->iommu[(addr & 0xf) >> 2]; + break; + case 0x20c ... 0x3ff: /* IOMMU flush */ + val = 0; + break; + case 0xc00 ... 0xc3f: /* PCI interrupt control */ + if (addr & 4) { + val = s->pci_irq_map[(addr & 0x3f) >> 3]; + } else { + val = 0; + } + break; + case 0x2000 ... 0x202f: /* PCI control */ + val = s->pci_control[(addr & 0x3f) >> 2]; + break; + case 0xf020 ... 0xf027: /* Reset control */ + if (addr & 4) { + val = s->reset_control; + } else { + val = 0; + } + break; + case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ + case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ + case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ + case 0xf000 ... 0xf01f: /* FFB config, memory control */ + /* we don't care */ default: val = 0; break; } + APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val); + return val; } -static CPUWriteMemoryFunc *apb_config_write[] = { - &apb_config_writel, - &apb_config_writel, - &apb_config_writel, +static const MemoryRegionOps apb_config_ops = { + .read = apb_config_readl, + .write = apb_config_writel, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUReadMemoryFunc *apb_config_read[] = { - &apb_config_readl, - &apb_config_readl, - &apb_config_readl, -}; +static void apb_pci_config_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) +{ + APBState *s = opaque; -static CPUWriteMemoryFunc *pci_apb_write[] = { - &pci_host_data_writeb, - &pci_host_data_writew, - &pci_host_data_writel, -}; + val = qemu_bswap_len(val, size); + APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val); + pci_data_write(s->bus, addr, val, size); +} -static CPUReadMemoryFunc *pci_apb_read[] = { - &pci_host_data_readb, - &pci_host_data_readw, - &pci_host_data_readl, -}; +static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr, + unsigned size) +{ + uint32_t ret; + APBState *s = opaque; + + ret = pci_data_read(s->bus, addr, size); + ret = qemu_bswap_len(ret, size); + APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret); + return ret; +} static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, uint32_t val) { - cpu_outb(NULL, addr & 0xffff, val); + cpu_outb(addr & IOPORTS_MASK, val); } static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, uint32_t val) { - cpu_outw(NULL, addr & 0xffff, val); + cpu_outw(addr & IOPORTS_MASK, bswap16(val)); } static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, uint32_t val) { - cpu_outl(NULL, addr & 0xffff, val); + cpu_outl(addr & IOPORTS_MASK, bswap32(val)); } static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) { uint32_t val; - val = cpu_inb(NULL, addr & 0xffff); + val = cpu_inb(addr & IOPORTS_MASK); return val; } @@ -175,7 +236,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) { uint32_t val; - val = cpu_inw(NULL, addr & 0xffff); + val = bswap16(cpu_inw(addr & IOPORTS_MASK)); return val; } @@ -183,20 +244,16 @@ static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) { uint32_t val; - val = cpu_inl(NULL, addr & 0xffff); + val = bswap32(cpu_inl(addr & IOPORTS_MASK)); return val; } -static CPUWriteMemoryFunc *pci_apb_iowrite[] = { - &pci_apb_iowriteb, - &pci_apb_iowritew, - &pci_apb_iowritel, -}; - -static CPUReadMemoryFunc *pci_apb_ioread[] = { - &pci_apb_ioreadb, - &pci_apb_ioreadw, - &pci_apb_ioreadl, +static const MemoryRegionOps pci_ioport_ops = { + .old_mmio = { + .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl }, + .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* The APB host has an IRQ line for each IRQ line of each slot. */ @@ -215,62 +272,206 @@ static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num) return bus_offset + irq_num; } -static void pci_apb_set_irq(qemu_irq *pic, int irq_num, int level) +static void pci_apb_set_irq(void *opaque, int irq_num, int level) { + APBState *s = opaque; + /* PCI IRQ map onto the first 32 INO. */ - qemu_set_irq(pic[irq_num], level); + if (irq_num < 32) { + if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { + APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level); + qemu_set_irq(s->pci_irqs[irq_num], level); + } else { + APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num); + qemu_irq_lower(s->pci_irqs[irq_num]); + } + } +} + +static int apb_pci_bridge_initfn(PCIDevice *dev) +{ + int rc; + + rc = pci_bridge_initfn(dev); + if (rc < 0) { + return rc; + } + + /* + * command register: + * According to PCI bridge spec, after reset + * bus master bit is off + * memory space enable bit is off + * According to manual (805-1251.pdf). + * the reset value should be zero unless the boot pin is tied high + * (which is true) and thus it should be PCI_COMMAND_MEMORY. + */ + pci_set_word(dev->config + PCI_COMMAND, + PCI_COMMAND_MEMORY); + pci_set_word(dev->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); + return 0; } PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, qemu_irq *pic, PCIBus **bus2, PCIBus **bus3) { - APBState *s; - PCIDevice *d; - int pci_mem_config, pci_mem_data, apb_config, pci_ioport; + DeviceState *dev; + SysBusDevice *s; + APBState *d; + unsigned int i; + PCIDevice *pci_dev; + PCIBridge *br; - s = qemu_mallocz(sizeof(APBState)); /* Ultrasparc PBM main bus */ - s->bus = pci_register_bus(pci_apb_set_irq, pci_pbm_map_irq, pic, 0, 32); - - pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read, - pci_apb_config_write, s); - apb_config = cpu_register_io_memory(0, apb_config_read, - apb_config_write, s); - pci_mem_data = cpu_register_io_memory(0, pci_apb_read, - pci_apb_write, s); - pci_ioport = cpu_register_io_memory(0, pci_apb_ioread, - pci_apb_iowrite, s); - - cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config); - cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, - pci_mem_config); - cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, - pci_ioport); - cpu_register_physical_memory(mem_base, 0x10000000, - pci_mem_data); // XXX size should be 4G-prom - - d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice), - 0, NULL, NULL); - d->config[0x00] = 0x8e; // vendor_id : Sun - d->config[0x01] = 0x10; - d->config[0x02] = 0x00; // device_id - d->config[0x03] = 0xa0; - d->config[0x04] = 0x06; // command = bus master, pci mem - d->config[0x05] = 0x00; - d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error - d->config[0x07] = 0x03; // status = medium devsel - d->config[0x08] = 0x00; // revision - d->config[0x09] = 0x00; // programming i/f - d->config[0x0A] = 0x00; // class_sub = pci host - d->config[0x0B] = 0x06; // class_base = PCI_bridge - d->config[0x0D] = 0x10; // latency_timer - d->config[0x0E] = 0x00; // header_type + dev = qdev_create(NULL, "pbm"); + qdev_init_nofail(dev); + s = sysbus_from_qdev(dev); + /* apb_config */ + sysbus_mmio_map(s, 0, special_base); + /* PCI configuration space */ + sysbus_mmio_map(s, 1, special_base + 0x1000000ULL); + /* pci_ioport */ + sysbus_mmio_map(s, 2, special_base + 0x2000000ULL); + d = FROM_SYSBUS(APBState, s); + + memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); + memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio); + + d->bus = pci_register_bus(&d->busdev.qdev, "pci", + pci_apb_set_irq, pci_pbm_map_irq, d, + &d->pci_mmio, + get_system_io(), + 0, 32); + + for (i = 0; i < 32; i++) { + sysbus_connect_irq(s, i, pic[i]); + } + + pci_create_simple(d->bus, 0, "pbm"); /* APB secondary busses */ - *bus2 = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq, - "Advanced PCI Bus secondary bridge 1"); - *bus3 = pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, - "Advanced PCI Bus secondary bridge 2"); - return s->bus; + pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true, + "pbm-bridge"); + br = DO_UPCAST(PCIBridge, dev, pci_dev); + pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1", + pci_apb_map_irq); + qdev_init_nofail(&pci_dev->qdev); + *bus2 = pci_bridge_get_sec_bus(br); + + pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true, + "pbm-bridge"); + br = DO_UPCAST(PCIBridge, dev, pci_dev); + pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2", + pci_apb_map_irq); + qdev_init_nofail(&pci_dev->qdev); + *bus3 = pci_bridge_get_sec_bus(br); + + return d->bus; +} + +static void pci_pbm_reset(DeviceState *d) +{ + unsigned int i; + APBState *s = container_of(d, APBState, busdev.qdev); + + for (i = 0; i < 8; i++) { + s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; + } + + if (s->nr_resets++ == 0) { + /* Power on reset */ + s->reset_control = POR; + } } + +static const MemoryRegionOps pci_config_ops = { + .read = apb_pci_config_read, + .write = apb_pci_config_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static int pci_pbm_init_device(SysBusDevice *dev) +{ + APBState *s; + unsigned int i; + + s = FROM_SYSBUS(APBState, dev); + for (i = 0; i < 8; i++) { + s->pci_irq_map[i] = (0x1f << 6) | (i << 2); + } + for (i = 0; i < 32; i++) { + sysbus_init_irq(dev, &s->pci_irqs[i]); + } + + /* apb_config */ + memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config", + 0x10000); + /* at region 0 */ + sysbus_init_mmio_region(dev, &s->apb_config); + + memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config", + 0x1000000); + /* at region 1 */ + sysbus_init_mmio_region(dev, &s->pci_config); + + /* pci_ioport */ + memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s, + "apb-pci-ioport", 0x10000); + /* at region 2 */ + sysbus_init_mmio_region(dev, &s->pci_ioport); + + return 0; +} + +static int pbm_pci_host_init(PCIDevice *d) +{ + pci_set_word(d->config + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_set_word(d->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); + return 0; +} + +static PCIDeviceInfo pbm_pci_host_info = { + .qdev.name = "pbm", + .qdev.size = sizeof(PCIDevice), + .init = pbm_pci_host_init, + .vendor_id = PCI_VENDOR_ID_SUN, + .device_id = PCI_DEVICE_ID_SUN_SABRE, + .class_id = PCI_CLASS_BRIDGE_HOST, + .is_bridge = 1, +}; + +static SysBusDeviceInfo pbm_host_info = { + .qdev.name = "pbm", + .qdev.size = sizeof(APBState), + .qdev.reset = pci_pbm_reset, + .init = pci_pbm_init_device, +}; + +static PCIDeviceInfo pbm_pci_bridge_info = { + .qdev.name = "pbm-bridge", + .qdev.size = sizeof(PCIBridge), + .qdev.vmsd = &vmstate_pci_device, + .qdev.reset = pci_bridge_reset, + .init = apb_pci_bridge_initfn, + .exit = pci_bridge_exitfn, + .vendor_id = PCI_VENDOR_ID_SUN, + .device_id = PCI_DEVICE_ID_SUN_SIMBA, + .revision = 0x11, + .config_write = pci_bridge_write_config, + .is_bridge = 1, +}; + +static void pbm_register_devices(void) +{ + sysbus_register_withprop(&pbm_host_info); + pci_qdev_register(&pbm_pci_host_info); + pci_qdev_register(&pbm_pci_bridge_info); +} + +device_init(pbm_register_devices)