X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/b92fa33486b240404923308b483a3318eb804c4a..b8031adba791325907d8a9e19af8d483996974fd:/target-s390x/insn-data.def?ds=sidebyside diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 00b95b681d..b42ebb6a1a 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -104,6 +104,9 @@ /* CHECKSUM */ C(0xb241, CKSM, RRE, Z, r1_o, ra2, new, r1_32, cksm, 0) +/* COPY SIGN */ + C(0xb372, CPSDR, RRF_b, FPSSH, f3_o, f2_o, f1, 0, cps, 0) + /* COMPARE */ C(0x1900, CR, RR_a, Z, r1_o, r2_o, 0, 0, 0, cmps32) C(0x5900, C, RX_a, Z, r1_o, m2_32s, 0, 0, 0, cmps32) @@ -190,13 +193,13 @@ D(0xec7d, CLGIJ, RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1) /* COMPARE AND SWAP */ - C(0xba00, CS, RS_a, Z, r1_o, a2, new, r1_32, cs, 0) - C(0xeb14, CSY, RSY_a, LD, r1_o, a2, new, r1_32, cs, 0) - C(0xeb30, CSG, RSY_a, Z, r1_o, a2, r1, 0, csg, 0) + D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, 0) + D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, 0) + D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, 1) /* COMPARE DOUBLE AND SWAP */ - C(0xbb00, CDS, RS_a, Z, r1_D32, a2, new, r1_D32, cds, 0) - C(0xeb31, CDSY, RSY_a, LD, r1_D32, a2, new, r1_D32, cds, 0) - C(0xeb3e, CDSG, RSY_a, Z, 0, a2, 0, 0, cdsg, 0) + D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, 1) + D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, 1) + C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) /* COMPARE AND TRAP */ D(0xb972, CRT, RRF_c, GIE, r1_32s, r2_32s, 0, 0, ct, 0, 0) @@ -226,6 +229,20 @@ C(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0) C(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, f1, 0, cdgb, 0) C(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, x1, 0, cxgb, 0) +/* CONVERT TO LOGICAL */ + C(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0) + C(0xb39d, CLFDBR, RRF_e, FPE, 0, f2_o, new, r1_32, clfdb, 0) + C(0xb39e, CLFXBR, RRF_e, FPE, 0, x2_o, new, r1_32, clfxb, 0) + C(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0) + C(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2_o, r1, 0, clgdb, 0) + C(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2_o, r1, 0, clgxb, 0) +/* CONVERT FROM LOGICAL */ + C(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0) + C(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, f1, 0, cdlgb, 0) + C(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, x1, 0, cxlgb, 0) + C(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0) + C(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, f1, 0, cdlgb, 0) + C(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, x1, 0, cxlgb, 0) /* DIVIDE */ C(0x1d00, DR, RR_a, Z, r1_D32, r2_32s, new_P, r1_P32, divs32, 0) @@ -254,7 +271,7 @@ C(0xb982, XGR, RRE, Z, r1, r2, r1, 0, xor, nz64) C(0xb9e7, XGRK, RRF_a, DO, r2, r3, r1, 0, xor, nz64) C(0xe382, XG, RXY_a, Z, r1, m2_64, r1, 0, xor, nz64) - C(0xd700, XC, SS_a, Z, la1, a2, 0, 0, xc, 0) + C(0xd700, XC, SS_a, Z, 0, 0, 0, 0, xc, 0) /* EXCLUSIVE OR IMMEDIATE */ D(0xc006, XIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2020) D(0xc007, XILF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2000) @@ -339,6 +356,7 @@ C(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32) C(0xb313, LCDBR, RRE, Z, 0, f2_o, f1, 0, negf64, f64) C(0xb343, LCXBR, RRE, Z, 0, x2_o, x1, 0, negf128, f128) + C(0xb373, LCDFR, RRE, FPSSH, 0, f2_o, f1, 0, negf64, 0) /* LOAD HALFWORD */ C(0xb927, LHR, RRE, EI, 0, r2_16s, 0, r1_32, mov2, 0) C(0xb907, LGHR, RRE, EI, 0, r2_16s, 0, r1, mov2, 0) @@ -415,6 +433,8 @@ /* LOAD FPC */ C(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0) +/* LOAD FPC AND SIGNAL */ + C(0xb2bd, LFAS, S, IEEEE_SIM, 0, m2_32u, 0, 0, sfas, 0) /* LOAD LENGTHENED */ C(0xb304, LDEBR, RRE, Z, 0, e2, f1, 0, ldeb, 0) @@ -525,6 +545,9 @@ C(0xe336, PFD, RXY_b, GIE, 0, 0, 0, 0, 0, 0) C(0xc602, PFDRL, RIL_c, GIE, 0, 0, 0, 0, 0, 0) +/* POPULATION COUNT */ + C(0xb9e1, POPCNT, RRE, PC, 0, r2_o, r1, 0, popcnt, nz64) + /* ROTATE LEFT SINGLE LOGICAL */ C(0xeb1d, RLL, RSY_a, Z, r3_o, sh32, new, r1_32, rll32, 0) C(0xeb1c, RLLG, RSY_a, Z, r3_o, sh64, r1, 0, rll64, 0) @@ -545,6 +568,13 @@ C(0xb24e, SAR, RRE, Z, 0, r2_o, 0, 0, sar, 0) /* SET FPC */ C(0xb384, SFPC, RRE, Z, 0, r1_o, 0, 0, sfpc, 0) +/* SET FPC AND SIGNAL */ + C(0xb385, SFASR, RRE, IEEEE_SIM, 0, r1_o, 0, 0, sfas, 0) +/* SET BFP ROUNDING MODE */ + C(0xb299, SRNM, S, Z, 0, 0, 0, 0, srnm, 0) + C(0xb2b8, SRNMB, S, FPE, 0, 0, 0, 0, srnm, 0) +/* SET DFP ROUNDING MODE */ + C(0xb2b9, SRNMT, S, DFP, 0, 0, 0, 0, srnm, 0) /* SHIFT LEFT SINGLE */ D(0x8b00, SLA, RS_a, Z, r1, sh32, new, r1_32, sla, 0, 31)