X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/7672725d41d1a04195affc1a7bd5676ba6314b14..e9854c39452b293f883c2e9e1d30c9930b5a2c49:/target-lm32/helper.c diff --git a/target-lm32/helper.c b/target-lm32/helper.c index d0bc1931d8..7a41f29730 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -1,7 +1,7 @@ /* * LatticeMico32 helper routines. * - * Copyright (c) 2010 Michael Walle + * Copyright (c) 2010-2014 Michael Walle * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -18,208 +18,206 @@ */ #include "cpu.h" -#include "host-utils.h" +#include "qemu/host-utils.h" +#include "sysemu/sysemu.h" -int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw, +int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; int prot; address &= TARGET_PAGE_MASK; prot = PAGE_BITS; if (env->flags & LM32_FLAG_IGNORE_MSB) { - tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx, + TARGET_PAGE_SIZE); } else { - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); } return 0; } -target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr) +hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - return addr & TARGET_PAGE_MASK; -} - -void do_interrupt(CPULM32State *env) -{ - qemu_log_mask(CPU_LOG_INT, - "exception at pc=%x type=%x\n", env->pc, env->exception_index); + LM32CPU *cpu = LM32_CPU(cs); - switch (env->exception_index) { - case EXCP_INSN_BUS_ERROR: - case EXCP_DATA_BUS_ERROR: - case EXCP_DIVIDE_BY_ZERO: - case EXCP_IRQ: - case EXCP_SYSTEMCALL: - /* non-debug exceptions */ - env->regs[R_EA] = env->pc; - env->ie |= (env->ie & IE_IE) ? IE_EIE : 0; - env->ie &= ~IE_IE; - if (env->dc & DC_RE) { - env->pc = env->deba + (env->exception_index * 32); - } else { - env->pc = env->eba + (env->exception_index * 32); - } - log_cpu_state_mask(CPU_LOG_INT, env, 0); - break; - case EXCP_BREAKPOINT: - case EXCP_WATCHPOINT: - /* debug exceptions */ - env->regs[R_BA] = env->pc; - env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; - env->ie &= ~IE_IE; - env->pc = env->deba + (env->exception_index * 32); - log_cpu_state_mask(CPU_LOG_INT, env, 0); - break; - default: - cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); - break; + addr &= TARGET_PAGE_MASK; + if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) { + return addr & 0x7fffffff; + } else { + return addr; } } -typedef struct { - const char *name; - uint32_t revision; - uint8_t num_interrupts; - uint8_t num_breakpoints; - uint8_t num_watchpoints; - uint32_t features; -} LM32Def; - -static const LM32Def lm32_defs[] = { - { - .name = "lm32-basic", - .revision = 3, - .num_interrupts = 32, - .num_breakpoints = 4, - .num_watchpoints = 4, - .features = (LM32_FEATURE_SHIFT - | LM32_FEATURE_SIGN_EXTEND - | LM32_FEATURE_CYCLE_COUNT), - }, - { - .name = "lm32-standard", - .revision = 3, - .num_interrupts = 32, - .num_breakpoints = 4, - .num_watchpoints = 4, - .features = (LM32_FEATURE_MULTIPLY - | LM32_FEATURE_DIVIDE - | LM32_FEATURE_SHIFT - | LM32_FEATURE_SIGN_EXTEND - | LM32_FEATURE_I_CACHE - | LM32_FEATURE_CYCLE_COUNT), - }, - { - .name = "lm32-full", - .revision = 3, - .num_interrupts = 32, - .num_breakpoints = 4, - .num_watchpoints = 4, - .features = (LM32_FEATURE_MULTIPLY - | LM32_FEATURE_DIVIDE - | LM32_FEATURE_SHIFT - | LM32_FEATURE_SIGN_EXTEND - | LM32_FEATURE_I_CACHE - | LM32_FEATURE_D_CACHE - | LM32_FEATURE_CYCLE_COUNT), - } -}; - -void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf) +void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address) { - int i; + LM32CPU *cpu = lm32_env_get_cpu(env); - cpu_fprintf(f, "Available CPUs:\n"); - for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) { - cpu_fprintf(f, " %s\n", lm32_defs[i].name); - } + cpu_breakpoint_insert(CPU(cpu), address, BP_CPU, + &env->cpu_breakpoint[idx]); } -static const LM32Def *cpu_lm32_find_by_name(const char *name) +void lm32_breakpoint_remove(CPULM32State *env, int idx) { - int i; + LM32CPU *cpu = lm32_env_get_cpu(env); - for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) { - if (strcasecmp(name, lm32_defs[i].name) == 0) { - return &lm32_defs[i]; - } + if (!env->cpu_breakpoint[idx]) { + return; } - return NULL; + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]); + env->cpu_breakpoint[idx] = NULL; } -static uint32_t cfg_by_def(const LM32Def *def) +void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, + lm32_wp_t wp_type) { - uint32_t cfg = 0; + LM32CPU *cpu = lm32_env_get_cpu(env); + int flags = 0; - if (def->features & LM32_FEATURE_MULTIPLY) { - cfg |= CFG_M; + switch (wp_type) { + case LM32_WP_DISABLED: + /* nothing to to */ + break; + case LM32_WP_READ: + flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ; + break; + case LM32_WP_WRITE: + flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE; + break; + case LM32_WP_READ_WRITE: + flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS; + break; } - if (def->features & LM32_FEATURE_DIVIDE) { - cfg |= CFG_D; + if (flags != 0) { + cpu_watchpoint_insert(CPU(cpu), address, 1, flags, + &env->cpu_watchpoint[idx]); } +} - if (def->features & LM32_FEATURE_SHIFT) { - cfg |= CFG_S; - } +void lm32_watchpoint_remove(CPULM32State *env, int idx) +{ + LM32CPU *cpu = lm32_env_get_cpu(env); - if (def->features & LM32_FEATURE_SIGN_EXTEND) { - cfg |= CFG_X; + if (!env->cpu_watchpoint[idx]) { + return; } - if (def->features & LM32_FEATURE_I_CACHE) { - cfg |= CFG_IC; - } + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]); + env->cpu_watchpoint[idx] = NULL; +} - if (def->features & LM32_FEATURE_D_CACHE) { - cfg |= CFG_DC; - } +static bool check_watchpoints(CPULM32State *env) +{ + LM32CPU *cpu = lm32_env_get_cpu(env); + int i; - if (def->features & LM32_FEATURE_CYCLE_COUNT) { - cfg |= CFG_CC; + for (i = 0; i < cpu->num_watchpoints; i++) { + if (env->cpu_watchpoint[i] && + env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { + return true; + } } - - cfg |= (def->num_interrupts << CFG_INT_SHIFT); - cfg |= (def->num_breakpoints << CFG_BP_SHIFT); - cfg |= (def->num_watchpoints << CFG_WP_SHIFT); - cfg |= (def->revision << CFG_REV_SHIFT); - - return cfg; + return false; } -CPULM32State *cpu_lm32_init(const char *cpu_model) +void lm32_debug_excp_handler(CPUState *cs) { - LM32CPU *cpu; - CPULM32State *env; - const LM32Def *def; - static int tcg_initialized; - - def = cpu_lm32_find_by_name(cpu_model); - if (!def) { - return NULL; + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; + CPUBreakpoint *bp; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; + if (check_watchpoints(env)) { + raise_exception(env, EXCP_WATCHPOINT); + } else { + cpu_resume_from_signal(cs, NULL); + } + } + } else { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc == env->pc) { + if (bp->flags & BP_CPU) { + raise_exception(env, EXCP_BREAKPOINT); + } + break; + } + } } +} - cpu = LM32_CPU(object_new(TYPE_LM32_CPU)); - env = &cpu->env; +void lm32_cpu_do_interrupt(CPUState *cs) +{ + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; - env->features = def->features; - env->num_bps = def->num_breakpoints; - env->num_wps = def->num_watchpoints; - env->cfg = cfg_by_def(def); + qemu_log_mask(CPU_LOG_INT, + "exception at pc=%x type=%x\n", env->pc, cs->exception_index); - qemu_init_vcpu(env); + switch (cs->exception_index) { + case EXCP_SYSTEMCALL: + if (unlikely(semihosting_enabled)) { + /* do_semicall() returns true if call was handled. Otherwise + * do the normal exception handling. */ + if (lm32_cpu_do_semihosting(cs)) { + env->pc += 4; + break; + } + } + /* fall through */ + case EXCP_INSN_BUS_ERROR: + case EXCP_DATA_BUS_ERROR: + case EXCP_DIVIDE_BY_ZERO: + case EXCP_IRQ: + /* non-debug exceptions */ + env->regs[R_EA] = env->pc; + env->ie |= (env->ie & IE_IE) ? IE_EIE : 0; + env->ie &= ~IE_IE; + if (env->dc & DC_RE) { + env->pc = env->deba + (cs->exception_index * 32); + } else { + env->pc = env->eba + (cs->exception_index * 32); + } + log_cpu_state_mask(CPU_LOG_INT, cs, 0); + break; + case EXCP_BREAKPOINT: + case EXCP_WATCHPOINT: + /* debug exceptions */ + env->regs[R_BA] = env->pc; + env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; + env->ie &= ~IE_IE; + env->pc = env->deba + (cs->exception_index * 32); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); + break; + default: + cpu_abort(cs, "unhandled exception type=%d\n", + cs->exception_index); + break; + } +} - if (tcg_enabled() && !tcg_initialized) { - tcg_initialized = 1; - lm32_translate_init(); +bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; + + if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) { + cs->exception_index = EXCP_IRQ; + lm32_cpu_do_interrupt(cs); + return true; } + return false; +} - return env; +LM32CPU *cpu_lm32_init(const char *cpu_model) +{ + return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); } /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory @@ -233,9 +231,3 @@ void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value) env->flags &= ~LM32_FLAG_IGNORE_MSB; } } - -void cpu_state_reset(CPULM32State *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} -