X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/74b728e4f3a4be43c71a58e4c8102b6d700a0018..1422e32db51ff2b1194fb24a6201c4310be5667d:/hw/omap1.c diff --git a/hw/omap1.c b/hw/omap1.c index 1aa5f2388b..4d5815eb08 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -26,7 +26,7 @@ #include "sysbus.h" /* Should signal the TCMI/GPMC */ -uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) +uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) { uint8_t ret; @@ -35,7 +35,7 @@ uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) return ret; } -void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, +void omap_badwidth_write8(void *opaque, hwaddr addr, uint32_t value) { uint8_t val8 = value; @@ -44,7 +44,7 @@ void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, cpu_physical_memory_write(addr, (void *) &val8, 1); } -uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) +uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) { uint16_t ret; @@ -53,7 +53,7 @@ uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) return ret; } -void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, +void omap_badwidth_write16(void *opaque, hwaddr addr, uint32_t value) { uint16_t val16 = value; @@ -62,7 +62,7 @@ void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, cpu_physical_memory_write(addr, (void *) &val16, 2); } -uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) +uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) { uint32_t ret; @@ -71,7 +71,7 @@ uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) return ret; } -void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, +void omap_badwidth_write32(void *opaque, hwaddr addr, uint32_t value) { OMAP_32B_REG(addr); @@ -176,7 +176,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) timer->rate = omap_clk_getrate(timer->clk); } -static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; @@ -200,7 +200,7 @@ static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_mpu_timer_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; @@ -251,7 +251,7 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) } static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, qemu_irq irq, omap_clk clk) { struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) @@ -282,7 +282,7 @@ struct omap_watchdog_timer_s { int reset; }; -static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, unsigned size) { struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; @@ -307,7 +307,7 @@ static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_wd_timer_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; @@ -380,7 +380,7 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) } static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, - target_phys_addr_t base, + hwaddr base, qemu_irq irq, omap_clk clk) { struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) @@ -405,7 +405,7 @@ struct omap_32khz_timer_s { MemoryRegion iomem; }; -static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, unsigned size) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; @@ -432,7 +432,7 @@ static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_os_timer_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; @@ -486,7 +486,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s) } static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, - target_phys_addr_t base, + hwaddr base, qemu_irq irq, omap_clk clk) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) @@ -506,7 +506,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, } /* Ultra Low-Power Device Module */ -static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -573,7 +573,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); } -static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, +static void omap_ulpd_pm_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -726,7 +726,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) } static void omap_ulpd_pm_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, struct omap_mpu_state_s *mpu) { memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu, @@ -736,7 +736,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory, } /* OMAP Pin Configuration */ -static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -843,7 +843,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); } -static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, +static void omap_pin_cfg_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -944,7 +944,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) } static void omap_pin_cfg_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, struct omap_mpu_state_s *mpu) { memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu, @@ -954,7 +954,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory, } /* Device Identification, Die Identification */ -static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_id_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1001,7 +1001,7 @@ static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_id_write(void *opaque, target_phys_addr_t addr, +static void omap_id_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { if (size != 4) { @@ -1035,7 +1035,7 @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) } /* MPUI Control (Dummy) */ -static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_mpui_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1068,7 +1068,7 @@ static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_mpui_write(void *opaque, target_phys_addr_t addr, +static void omap_mpui_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1109,7 +1109,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s) s->mpui_ctrl = 0x0003ff1b; } -static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base, +static void omap_mpui_init(MemoryRegion *memory, hwaddr base, struct omap_mpu_state_s *mpu) { memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu, @@ -1131,7 +1131,7 @@ struct omap_tipb_bridge_s { uint16_t enh_control; }; -static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, unsigned size) { struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; @@ -1161,7 +1161,7 @@ static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, +static void omap_tipb_bridge_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; @@ -1215,7 +1215,7 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) } static struct omap_tipb_bridge_s *omap_tipb_bridge_init( - MemoryRegion *memory, target_phys_addr_t base, + MemoryRegion *memory, hwaddr base, qemu_irq abort_irq, omap_clk clk) { struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) @@ -1232,7 +1232,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init( } /* Dummy Traffic Controller's Memory Interface */ -static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1270,7 +1270,7 @@ static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, +static void omap_tcmi_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1330,7 +1330,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) mpu->tcmi_regs[0x40 >> 2] = 0x00000000; } -static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base, +static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, struct omap_mpu_state_s *mpu) { memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu, @@ -1346,7 +1346,7 @@ struct dpll_ctl_s { omap_clk dpll; }; -static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_dpll_read(void *opaque, hwaddr addr, unsigned size) { struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; @@ -1362,7 +1362,7 @@ static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_dpll_write(void *opaque, target_phys_addr_t addr, +static void omap_dpll_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; @@ -1412,7 +1412,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s) } static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, - target_phys_addr_t base, omap_clk clk) + hwaddr base, omap_clk clk) { struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100); @@ -1425,7 +1425,7 @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, } /* MPU Clock/Reset/Power Mode Control */ -static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_clkm_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1519,8 +1519,9 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, { omap_clk clk; - if (value & (1 << 11)) /* SETARM_IDLE */ - cpu_interrupt(s->env, CPU_INTERRUPT_HALT); + if (value & (1 << 11)) { /* SETARM_IDLE */ + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); + } if (!(value & (1 << 10))) /* WKUP_MODE */ qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ @@ -1626,7 +1627,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, } } -static void omap_clkm_write(void *opaque, target_phys_addr_t addr, +static void omap_clkm_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1713,7 +1714,7 @@ static const MemoryRegionOps omap_clkm_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1734,7 +1735,7 @@ static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr, case 0x18: /* DSP_SYSST */ return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | - (s->env->halted << 6); /* Quite useless... */ + (s->cpu->env.halted << 6); /* Quite useless... */ } OMAP_BAD_REG(addr); @@ -1757,7 +1758,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ } -static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, +static void omap_clkdsp_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1822,8 +1823,8 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s) s->clkm.dsp_rstct2 = 0x0000; } -static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base, - target_phys_addr_t dsp_base, struct omap_mpu_state_s *s) +static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, + hwaddr dsp_base, struct omap_mpu_state_s *s) { memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s, "omap-clkm", 0x100); @@ -1902,7 +1903,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) s->row_latch = ~rows; } -static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; @@ -1962,7 +1963,7 @@ static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, +static void omap_mpuio_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; @@ -2071,7 +2072,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int on) } static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, - target_phys_addr_t base, + hwaddr base, qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, omap_clk clk) { @@ -2158,7 +2159,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s) } } -static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size) { struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; @@ -2192,7 +2193,7 @@ static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_uwire_write(void *opaque, target_phys_addr_t addr, +static void omap_uwire_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; @@ -2262,7 +2263,7 @@ static void omap_uwire_reset(struct omap_uwire_s *s) } static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, qemu_irq txirq, qemu_irq rxirq, qemu_irq dma, omap_clk clk) @@ -2311,7 +2312,7 @@ static void omap_pwl_update(struct omap_pwl_s *s) } } -static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size) { struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; @@ -2331,7 +2332,7 @@ static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_pwl_write(void *opaque, target_phys_addr_t addr, +static void omap_pwl_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; @@ -2380,7 +2381,7 @@ static void omap_pwl_clk_update(void *opaque, int line, int on) } static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, omap_clk clk) { struct omap_pwl_s *s = g_malloc0(sizeof(*s)); @@ -2404,7 +2405,7 @@ struct omap_pwt_s { omap_clk clk; }; -static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size) { struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; @@ -2426,7 +2427,7 @@ static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_pwt_write(void *opaque, target_phys_addr_t addr, +static void omap_pwt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; @@ -2487,7 +2488,7 @@ static void omap_pwt_reset(struct omap_pwt_s *s) } static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, omap_clk clk) { struct omap_pwt_s *s = g_malloc0(sizeof(*s)); @@ -2535,7 +2536,7 @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s) printf("%s: conversion failed\n", __FUNCTION__); } -static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size) { struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; @@ -2617,7 +2618,7 @@ static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_rtc_write(void *opaque, target_phys_addr_t addr, +static void omap_rtc_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; @@ -2888,7 +2889,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s) s->pm_am = 0; s->auto_comp = 0; s->round = 0; - s->tick = qemu_get_clock_ms(rt_clock); + s->tick = qemu_get_clock_ms(rtc_clock); memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); s->alarm_tm.tm_mday = 0x01; s->status = 1 << 7; @@ -2900,7 +2901,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s) } static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, qemu_irq timerirq, qemu_irq alarmirq, omap_clk clk) { @@ -2909,7 +2910,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, s->irq = timerirq; s->alarm = alarmirq; - s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s); + s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s); omap_rtc_reset(s); @@ -3128,7 +3129,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) omap_mcbsp_rx_stop(s); } -static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; @@ -3226,7 +3227,7 @@ static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, +static void omap_mcbsp_writeh(void *opaque, hwaddr addr, uint32_t value) { struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; @@ -3364,7 +3365,7 @@ static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, OMAP_BAD_REG(addr); } -static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, +static void omap_mcbsp_writew(void *opaque, hwaddr addr, uint32_t value) { struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; @@ -3395,7 +3396,7 @@ static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, omap_badwidth_write16(opaque, addr, value); } -static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr, +static void omap_mcbsp_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { switch (size) { @@ -3431,7 +3432,7 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s) } static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, - target_phys_addr_t base, + hwaddr base, qemu_irq txirq, qemu_irq rxirq, qemu_irq *dma, omap_clk clk) { @@ -3497,9 +3498,9 @@ static void omap_lpg_tick(void *opaque) struct omap_lpg_s *s = opaque; if (s->cycle) - qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on); + qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->period - s->on); else - qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on); + qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->on); s->cycle = !s->cycle; printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); @@ -3546,7 +3547,7 @@ static void omap_lpg_reset(struct omap_lpg_s *s) omap_lpg_update(s); } -static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size) { struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; @@ -3568,7 +3569,7 @@ static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_lpg_write(void *opaque, target_phys_addr_t addr, +static void omap_lpg_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; @@ -3612,12 +3613,12 @@ static void omap_lpg_clk_update(void *opaque, int line, int on) } static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, - target_phys_addr_t base, omap_clk clk) + hwaddr base, omap_clk clk) { struct omap_lpg_s *s = (struct omap_lpg_s *) g_malloc0(sizeof(struct omap_lpg_s)); - s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s); + s->tm = qemu_new_timer_ms(vm_clock, omap_lpg_tick, s); omap_lpg_reset(s); @@ -3630,7 +3631,7 @@ static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, } /* MPUI Peripheral Bridge configuration */ -static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr, +static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, unsigned size) { if (size != 2) { @@ -3644,7 +3645,7 @@ static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr, return 0; } -static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr, +static void omap_mpui_io_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { /* FIXME: infinite loop */ @@ -3694,7 +3695,6 @@ static void omap1_mpu_reset(void *opaque) omap_uwire_reset(mpu->microwire); omap_pwl_reset(mpu->pwl); omap_pwt_reset(mpu->pwt); - omap_i2c_reset(mpu->i2c[0]); omap_rtc_reset(mpu->rtc); omap_mcbsp_reset(mpu->mcbsp1); omap_mcbsp_reset(mpu->mcbsp2); @@ -3702,12 +3702,12 @@ static void omap1_mpu_reset(void *opaque) omap_lpg_reset(mpu->led[0]); omap_lpg_reset(mpu->led[1]); omap_clkm_reset(mpu); - cpu_reset(mpu->env); + cpu_reset(CPU(mpu->cpu)); } static const struct omap_map_s { - target_phys_addr_t phys_dsp; - target_phys_addr_t phys_mpu; + hwaddr phys_dsp; + hwaddr phys_mpu; uint32_t size; const char *name; } omap15xx_dsp_mm[] = { @@ -3752,8 +3752,9 @@ void omap_mpu_wakeup(void *opaque, int irq, int req) { struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; - if (mpu->env->halted) - cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); + if (mpu->cpu->env.halted) { + cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB); + } } static const struct dma_irq_map omap1_dma_irq_map[] = { @@ -3777,38 +3778,38 @@ static const struct dma_irq_map omap1_dma_irq_map[] = { /* DMA ports for OMAP1 */ static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + hwaddr addr) { return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); } static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + hwaddr addr) { return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, addr); } static int omap_validate_imif_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + hwaddr addr) { return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); } static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + hwaddr addr) { return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); } static int omap_validate_local_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + hwaddr addr) { return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); } static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + hwaddr addr) { return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); } @@ -3830,8 +3831,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, /* Core */ s->mpu_model = omap310; - s->env = cpu_init(core); - if (!s->env) { + s->cpu = cpu_arm_init(core); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -3853,7 +3854,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); - cpu_irq = arm_pic_init_cpu(s->env); + cpu_irq = arm_pic_init_cpu(s->cpu); s->ih[0] = qdev_create(NULL, "omap-intc"); qdev_prop_set_uint32(s->ih[0], "size", 0x100); qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); @@ -3993,9 +3994,15 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, s->pwt = omap_pwt_init(system_memory, 0xfffb6000, omap_findclk(s, "armxor_ck")); - s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800, - qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C), - &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck")); + s->i2c[0] = qdev_create(NULL, "omap_i2c"); + qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); + qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); + qdev_init_nofail(s->i2c[0]); + busdev = sysbus_from_qdev(s->i2c[0]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); + sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); + sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); + sysbus_mmio_map(busdev, 0, 0xfffb3800); s->rtc = omap_rtc_init(system_memory, 0xfffb4800, qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),