X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/5a1f7f44cf7a55b696859d09af1b18c8e40c8339..d70414a5788c3d51f8ce4d2f437e669e6b99dc59:/cpu-exec.c diff --git a/cpu-exec.c b/cpu-exec.c index 7efcf2761f..2ffeb6e40d 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -24,6 +24,9 @@ #include "qemu/atomic.h" #include "sysemu/qtest.h" #include "qemu/timer.h" +#include "exec/address-spaces.h" +#include "exec/memory-internal.h" +#include "qemu/rcu.h" /* -icount align implementation. */ @@ -61,8 +64,7 @@ static void align_clocks(SyncClocks *sc, const CPUState *cpu) sleep_delay.tv_sec = sc->diff_clk / 1000000000LL; sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL; if (nanosleep(&sleep_delay, &rem_delay) < 0) { - sc->diff_clk -= (sleep_delay.tv_sec - rem_delay.tv_sec) * 1000000000LL; - sc->diff_clk -= sleep_delay.tv_nsec - rem_delay.tv_nsec; + sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec; } else { sc->diff_clk = 0; } @@ -101,10 +103,8 @@ static void init_delay_params(SyncClocks *sc, if (!icount_align_option) { return; } - sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); - sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - - sc->realtime_clock + - cpu_get_clock_offset(); + sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); + sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay = sc->diff_clk; @@ -144,6 +144,33 @@ void cpu_resume_from_signal(CPUState *cpu, void *puc) cpu->exception_index = -1; siglongjmp(cpu->jmp_env, 1); } + +void cpu_reload_memory_map(CPUState *cpu) +{ + AddressSpaceDispatch *d; + + if (qemu_in_vcpu_thread()) { + /* Do not let the guest prolong the critical section as much as it + * as it desires. + * + * Currently, this is prevented by the I/O thread's periodinc kicking + * of the VCPU thread (iothread_requesting_mutex, qemu_cpu_kick_thread) + * but this will go away once TCG's execution moves out of the global + * mutex. + * + * This pair matches cpu_exec's rcu_read_lock()/rcu_read_unlock(), which + * only protects cpu->as->dispatch. Since we reload it below, we can + * split the critical section. + */ + rcu_read_unlock(); + rcu_read_lock(); + } + + /* The CPU and TLB are protected by the iothread lock. */ + d = atomic_rcu_read(&cpu->as->dispatch); + cpu->memory_dispatch = d; + tlb_flush(cpu, 1); +} #endif /* Execute a TB, and fix up the CPU state afterwards if necessary */ @@ -168,7 +195,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) } #endif /* DEBUG_DISAS */ + cpu->can_do_io = 0; next_tb = tcg_qemu_tb_exec(env, tb_ptr); + cpu->can_do_io = 1; trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK), next_tb & TB_EXIT_MASK); @@ -202,14 +231,19 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, { CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; + target_ulong pc = orig_tb->pc; + target_ulong cs_base = orig_tb->cs_base; + uint64_t flags = orig_tb->flags; /* Should never happen. We only end up here when an existing TB is too long. */ if (max_cycles > CF_COUNT_MASK) max_cycles = CF_COUNT_MASK; - tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, - max_cycles); + /* tb_gen_code can flush our orig_tb, invalidate it now */ + tb_phys_invalidate(orig_tb, -1); + tb = tb_gen_code(cpu, pc, cs_base, flags, + max_cycles | CF_NOCACHE); cpu->current_tb = tb; /* execute the generated code */ trace_exec_tb_nocache(tb, tb->pc); @@ -348,12 +382,13 @@ int cpu_exec(CPUArchState *env) * an instruction scheduling constraint on modern architectures. */ smp_mb(); + rcu_read_lock(); + if (unlikely(exit_request)) { cpu->exit_request = 1; } cc->cpu_exec_enter(cpu); - cpu->exception_index = -1; /* Calculate difference between guest clock and host clock. * This delay includes the delay of the last cycle, so @@ -373,6 +408,7 @@ int cpu_exec(CPUArchState *env) if (ret == EXCP_DEBUG) { cpu_handle_debug_exception(env); } + cpu->exception_index = -1; break; } else { #if defined(CONFIG_USER_ONLY) @@ -383,6 +419,7 @@ int cpu_exec(CPUArchState *env) cc->do_interrupt(cpu); #endif ret = cpu->exception_index; + cpu->exception_index = -1; break; #else cc->do_interrupt(cpu); @@ -404,17 +441,12 @@ int cpu_exec(CPUArchState *env) cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(cpu); } -#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ - defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ - defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || \ - defined(TARGET_UNICORE32) || defined(TARGET_TRICORE) if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; cpu_loop_exit(cpu); } -#endif #if defined(TARGET_I386) if (interrupt_request & CPU_INTERRUPT_INIT) { cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); @@ -426,209 +458,6 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_RESET) { cpu_reset(cpu); } -#endif -#if defined(TARGET_I386) -#if !defined(CONFIG_USER_ONLY) - if (interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; - apic_poll_irq(x86_cpu->apic_state); - } -#endif - if (interrupt_request & CPU_INTERRUPT_SIPI) { - do_cpu_sipi(x86_cpu); - } else if (env->hflags2 & HF2_GIF_MASK) { - if ((interrupt_request & CPU_INTERRUPT_SMI) && - !(env->hflags & HF_SMM_MASK)) { - cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, - 0); - cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; - do_smm_enter(x86_cpu); - next_tb = 0; - } else if ((interrupt_request & CPU_INTERRUPT_NMI) && - !(env->hflags2 & HF2_NMI_MASK)) { - cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; - env->hflags2 |= HF2_NMI_MASK; - do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); - next_tb = 0; - } else if (interrupt_request & CPU_INTERRUPT_MCE) { - cpu->interrupt_request &= ~CPU_INTERRUPT_MCE; - do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); - next_tb = 0; - } else if ((interrupt_request & CPU_INTERRUPT_HARD) && - (((env->hflags2 & HF2_VINTR_MASK) && - (env->hflags2 & HF2_HIF_MASK)) || - (!(env->hflags2 & HF2_VINTR_MASK) && - (env->eflags & IF_MASK && - !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { - int intno; - cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, - 0); - cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_VIRQ); - intno = cpu_get_pic_interrupt(env); - qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - /* ensure that no TB jump will be modified as - the program flow was changed */ - next_tb = 0; -#if !defined(CONFIG_USER_ONLY) - } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && - (env->eflags & IF_MASK) && - !(env->hflags & HF_INHIBIT_IRQ_MASK)) { - int intno; - /* FIXME: this should respect TPR */ - cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, - 0); - intno = ldl_phys(cpu->as, - env->vm_vmcb - + offsetof(struct vmcb, - control.int_vector)); - qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - next_tb = 0; -#endif - } - } -#elif defined(TARGET_PPC) - if (interrupt_request & CPU_INTERRUPT_HARD) { - ppc_hw_interrupt(env); - if (env->pending_interrupts == 0) { - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; - } - next_tb = 0; - } -#elif defined(TARGET_LM32) - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->ie & IE_IE)) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_MICROBLAZE) - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sregs[SR_MSR] & MSR_IE) - && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) - && !(env->iflags & (D_FLAG | IMM_FLAG))) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_MIPS) - if ((interrupt_request & CPU_INTERRUPT_HARD) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cpu->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_TRICORE) - if ((interrupt_request & CPU_INTERRUPT_HARD)) { - cc->do_interrupt(cpu); - next_tb = 0; - } - -#elif defined(TARGET_OPENRISC) - { - int idx = -1; - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sr & SR_IEE)) { - idx = EXCP_INT; - } - if ((interrupt_request & CPU_INTERRUPT_TIMER) - && (env->sr & SR_TEE)) { - idx = EXCP_TICK; - } - if (idx >= 0) { - cpu->exception_index = idx; - cc->do_interrupt(cpu); - next_tb = 0; - } - } -#elif defined(TARGET_SPARC) - if (interrupt_request & CPU_INTERRUPT_HARD) { - if (cpu_interrupts_enabled(env) && - env->interrupt_index > 0) { - int pil = env->interrupt_index & 0xf; - int type = env->interrupt_index & 0xf0; - - if (((type == TT_EXTINT) && - cpu_pil_allowed(env, pil)) || - type != TT_EXTINT) { - cpu->exception_index = env->interrupt_index; - cc->do_interrupt(cpu); - next_tb = 0; - } - } - } -#elif defined(TARGET_ARM) - if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->daif & PSTATE_F)) { - cpu->exception_index = EXCP_FIQ; - cc->do_interrupt(cpu); - next_tb = 0; - } - /* ARMv7-M interrupt return works by loading a magic value - into the PC. On real hardware the load causes the - return to occur. The qemu implementation performs the - jump normally, then does the exception return when the - CPU tries to execute code at the magic address. - This will cause the magic PC value to be pushed to - the stack if an interrupt occurred at the wrong time. - We avoid this by disabling interrupts when - pc contains a magic address. */ - if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->daif & PSTATE_I) - && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_UNICORE32) - if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->uncached_asr & ASR_I)) { - cpu->exception_index = UC32_EXCP_INTR; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_SH4) - if (interrupt_request & CPU_INTERRUPT_HARD) { - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_ALPHA) - { - int idx = -1; - /* ??? This hard-codes the OSF/1 interrupt levels. */ - switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { - case 0 ... 3: - if (interrupt_request & CPU_INTERRUPT_HARD) { - idx = EXCP_DEV_INTERRUPT; - } - /* FALLTHRU */ - case 4: - if (interrupt_request & CPU_INTERRUPT_TIMER) { - idx = EXCP_CLK_INTERRUPT; - } - /* FALLTHRU */ - case 5: - if (interrupt_request & CPU_INTERRUPT_SMP) { - idx = EXCP_SMP_INTERRUPT; - } - /* FALLTHRU */ - case 6: - if (interrupt_request & CPU_INTERRUPT_MCHK) { - idx = EXCP_MCHK; - } - } - if (idx >= 0) { - cpu->exception_index = idx; - env->error_code = 0; - cc->do_interrupt(cpu); - next_tb = 0; - } - } #endif /* The target hook has 3 exit conditions: False when the interrupt isn't processed, @@ -697,28 +526,22 @@ int cpu_exec(CPUArchState *env) * interrupt_request) which we will handle * next time around the loop. */ - tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); next_tb = 0; break; case TB_EXIT_ICOUNT_EXPIRED: { /* Instruction counter expired. */ - int insns_left; - tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); - insns_left = cpu->icount_decr.u32; + int insns_left = cpu->icount_decr.u32; if (cpu->icount_extra && insns_left >= 0) { /* Refill decrementer and continue execution. */ cpu->icount_extra += insns_left; - if (cpu->icount_extra > 0xffff) { - insns_left = 0xffff; - } else { - insns_left = cpu->icount_extra; - } + insns_left = MIN(0xffff, cpu->icount_extra); cpu->icount_extra -= insns_left; cpu->icount_decr.u16.low = insns_left; } else { if (insns_left > 0) { /* Execute remaining instructions. */ + tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); cpu_exec_nocache(env, insns_left, tb); align_clocks(&sc, cpu); } @@ -745,6 +568,7 @@ int cpu_exec(CPUArchState *env) cpu = current_cpu; env = cpu->env_ptr; cc = CPU_GET_CLASS(cpu); + cpu->can_do_io = 1; #ifdef TARGET_I386 x86_cpu = X86_CPU(cpu); #endif @@ -756,6 +580,7 @@ int cpu_exec(CPUArchState *env) } /* for(;;) */ cc->cpu_exec_exit(cpu); + rcu_read_unlock(); /* fail safe : never use current_cpu outside cpu_exec() */ current_cpu = NULL;