X-Git-Url: https://repo.jachan.dev/qemu.git/blobdiff_plain/3737c0541a8fa0afe492cc95453840c90cc7eb77..8e31bf388e56e5babd9600b110a94381d1be07b1:/hw/pl061.c diff --git a/hw/pl061.c b/hw/pl061.c index 7b1b636e9b..79e5c53e89 100644 --- a/hw/pl061.c +++ b/hw/pl061.c @@ -5,7 +5,7 @@ * Copyright (c) 2007 CodeSourcery. * Written by Paul Brook * - * This code is licenced under the GPL. + * This code is licensed under the GPL. */ #include "sysbus.h" @@ -24,6 +24,8 @@ do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) #endif static const uint8_t pl061_id[12] = + { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; +static const uint8_t pl061_id_luminary[12] = { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; typedef struct { @@ -50,6 +52,7 @@ typedef struct { uint8_t float_high; qemu_irq irq; qemu_irq out[8]; + const unsigned char *id; } pl061_state; static void pl061_update(pl061_state *s) @@ -83,7 +86,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset) pl061_state *s = (pl061_state *)opaque; if (offset >= 0xfd0 && offset < 0x1000) { - return pl061_id[(offset - 0xfd0) >> 2]; + return s->id[(offset - 0xfd0) >> 2]; } if (offset < 0x400) { return s->data & (offset >> 2); @@ -95,7 +98,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset) return s->isense; case 0x408: /* Interrupt both edges */ return s->ibe; - case 0x40c: /* Interupt event */ + case 0x40c: /* Interrupt event */ return s->iev; case 0x410: /* Interrupt mask */ return s->im; @@ -153,7 +156,7 @@ static void pl061_write(void *opaque, target_phys_addr_t offset, case 0x408: /* Interrupt both edges */ s->ibe = value; break; - case 0x40c: /* Interupt event */ + case 0x40c: /* Interrupt event */ s->iev = value; break; case 0x410: /* Interrupt mask */ @@ -291,26 +294,39 @@ static int pl061_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static int pl061_init(SysBusDevice *dev) +static int pl061_init(SysBusDevice *dev, const unsigned char *id) { int iomemtype; pl061_state *s = FROM_SYSBUS(pl061_state, dev); - + s->id = id; iomemtype = cpu_register_io_memory(pl061_readfn, - pl061_writefn, s); + pl061_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8); qdev_init_gpio_out(&dev->qdev, s->out, 8); pl061_reset(s); - register_savevm("pl061_gpio", -1, 1, pl061_save, pl061_load, s); + register_savevm(&dev->qdev, "pl061_gpio", -1, 1, pl061_save, pl061_load, s); return 0; } +static int pl061_init_luminary(SysBusDevice *dev) +{ + return pl061_init(dev, pl061_id_luminary); +} + +static int pl061_init_arm(SysBusDevice *dev) +{ + return pl061_init(dev, pl061_id); +} + static void pl061_register_devices(void) { sysbus_register_dev("pl061", sizeof(pl061_state), - pl061_init); + pl061_init_arm); + sysbus_register_dev("pl061_luminary", sizeof(pl061_state), + pl061_init_luminary); } device_init(pl061_register_devices)