SH4: Serial controller improvement

[qemu.git] / hw / apb_pci.c

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index fe9189247e6c7c84f95cc2367d881bd37d4ff54c..b56bb0733f1ac9a5c8a0598878851065a89fc013 100644 (file)
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -26,7 +26,8 @@
    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
    the secondary PCI bridge.  */
 
-#include "vl.h"
+#include "hw.h"
+#include "pci.h"
 typedef target_phys_addr_t pci_addr_t;
 #include "pci_host.h"
 
@@ -229,9 +230,12 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
                                           pci_apb_iowrite, s);
 
     cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);
-    cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config);
-    cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
-    cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
+    cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10,
+                                 pci_mem_config);
+    cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000,
+                                 pci_ioport);
+    cpu_register_physical_memory(mem_base, 0x10000000,
+                                 pci_mem_data); // XXX size should be 4G-prom
 
     d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
                             0, NULL, NULL);
@@ -251,8 +255,10 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
     d->config[0x0E] = 0x00; // header_type
 
     /* APB secondary busses */
-    secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 1");
-    pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 2");
+    secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq,
+                                "Advanced PCI Bus secondary bridge 1");
+    pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq,
+                    "Advanced PCI Bus secondary bridge 2");
     return secondary;
 }