+static void dummy_isa_irq_handler(void *opaque, int n, int level)
+{
+}
+
+/* EBUS (Eight bit bus) bridge */
+static void
+pci_ebus_init(PCIBus *bus, int devfn)
+{
+ qemu_irq *isa_irq;
+
+ pci_create_simple(bus, devfn, "ebus");
+ isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
+ isa_bus_irqs(isa_irq);
+}
+
+static int
+pci_ebus_init1(PCIDevice *s)
+{
+ isa_bus_new(&s->qdev);
+
+ pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
+ pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
+ s->config[0x04] = 0x06; // command = bus master, pci mem
+ s->config[0x05] = 0x00;
+ s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
+ s->config[0x07] = 0x03; // status = medium devsel
+ s->config[0x08] = 0x01; // revision
+ s->config[0x09] = 0x00; // programming i/f
+ pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
+ s->config[0x0D] = 0x0a; // latency_timer
+ s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
+ ebus_mmio_mapfunc);
+ pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM,
+ ebus_mmio_mapfunc);
+ return 0;
+}
+
+static PCIDeviceInfo ebus_info = {
+ .qdev.name = "ebus",
+ .qdev.size = sizeof(PCIDevice),
+ .init = pci_ebus_init1,
+};
+
+static void pci_ebus_register(void)
+{
+ pci_qdev_register(&ebus_info);
+}
+
+device_init(pci_ebus_register);
+
+/* Boot PROM (OpenBIOS) */
+static void prom_init(target_phys_addr_t addr, const char *bios_name)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *filename;
+ int ret;
+
+ dev = qdev_create(NULL, "openprom");
+ qdev_init(dev);
+ s = sysbus_from_qdev(dev);
+
+ sysbus_mmio_map(s, 0, addr);
+
+ /* load boot prom */
+ if (bios_name == NULL) {
+ bios_name = PROM_FILENAME;
+ }
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
+ 1, ELF_MACHINE, 0);
+ if (ret < 0 || ret > PROM_SIZE_MAX) {
+ ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
+ }
+ qemu_free(filename);
+ } else {
+ ret = -1;
+ }
+ if (ret < 0 || ret > PROM_SIZE_MAX) {
+ fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
+ exit(1);
+ }
+}
+
+static int prom_init1(SysBusDevice *dev)
+{
+ ram_addr_t prom_offset;
+
+ prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
+ sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
+ return 0;
+}
+
+static SysBusDeviceInfo prom_info = {
+ .init = prom_init1,
+ .qdev.name = "openprom",
+ .qdev.size = sizeof(SysBusDevice),
+ .qdev.props = (Property[]) {
+ {/* end of property list */}
+ }
+};
+
+static void prom_register_devices(void)
+{
+ sysbus_register_withprop(&prom_info);
+}
+
+device_init(prom_register_devices);
+
+
+typedef struct RamDevice
+{
+ SysBusDevice busdev;
+ uint64_t size;
+} RamDevice;
+
+/* System RAM */
+static int ram_init1(SysBusDevice *dev)
+{
+ ram_addr_t RAM_size, ram_offset;
+ RamDevice *d = FROM_SYSBUS(RamDevice, dev);
+
+ RAM_size = d->size;
+
+ ram_offset = qemu_ram_alloc(RAM_size);
+ sysbus_init_mmio(dev, RAM_size, ram_offset);
+ return 0;
+}
+
+static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+ RamDevice *d;
+
+ /* allocate RAM */
+ dev = qdev_create(NULL, "memory");
+ s = sysbus_from_qdev(dev);
+
+ d = FROM_SYSBUS(RamDevice, s);
+ d->size = RAM_size;
+ qdev_init(dev);
+
+ sysbus_mmio_map(s, 0, addr);
+}
+
+static SysBusDeviceInfo ram_info = {
+ .init = ram_init1,
+ .qdev.name = "memory",
+ .qdev.size = sizeof(RamDevice),
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT64("size", RamDevice, size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void ram_register_devices(void)
+{
+ sysbus_register_withprop(&ram_info);
+}
+
+device_init(ram_register_devices);
+
+static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
projects / qemu.git / blobdiff