* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/boards.h"
#include "hw/hw.h"
#include "hw/arm/arm.h"
#include "hw/arm/omap.h"
#include "sysemu/sysemu.h"
#include "hw/arm/soc_dma.h"
+#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "qemu/range.h"
#include "hw/sysbus.h"
+#include "qemu/cutils.h"
+#include "qemu/bcd.h"
/* Should signal the TCMI/GPMC */
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
{
- uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
+ uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
if (timer->st && timer->enable && timer->rate)
return timer->val - muldiv64(distance >> (timer->ptv + 1),
- timer->rate, get_ticks_per_sec());
+ timer->rate, NANOSECONDS_PER_SECOND);
else
return timer->val;
}
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
{
timer->val = omap_timer_read(timer);
- timer->time = qemu_get_clock_ns(vm_clock);
+ timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
if (timer->enable && timer->st && timer->rate) {
timer->val = timer->reset_val; /* Should skip this on clk enable */
expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
- get_ticks_per_sec(), timer->rate);
+ NANOSECONDS_PER_SECOND, timer->rate);
/* If timer expiry would be sooner than in about 1 ms and
* auto-reload isn't set, then fire immediately. This is a hack
* sets the interval to a very low value and polls the status bit
* in a busy loop when it wants to sleep just a couple of CPU
* ticks. */
- if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
- qemu_mod_timer(timer->timer, timer->time + expires);
- else
+ if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) {
+ timer_mod(timer->timer, timer->time + expires);
+ } else {
qemu_bh_schedule(timer->tick);
+ }
} else
- qemu_del_timer(timer->timer);
+ timer_del(timer->timer);
}
static void omap_timer_fire(void *opaque)
static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
{
omap_clk_adduser(timer->clk,
- qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
+ qemu_allocate_irq(omap_timer_clk_update, timer, 0));
timer->rate = omap_clk_getrate(timer->clk);
}
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
if (size != 4) {
- return omap_badwidth_write32(opaque, addr, value);
+ omap_badwidth_write32(opaque, addr, value);
+ return;
}
switch (addr) {
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
{
- qemu_del_timer(s->timer);
+ timer_del(s->timer);
s->enable = 0;
s->reset_val = 31337;
s->val = 0;
hwaddr base,
qemu_irq irq, omap_clk clk)
{
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
- g_malloc0(sizeof(struct omap_mpu_timer_s));
+ struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
s->irq = irq;
s->clk = clk;
- s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
s->tick = qemu_bh_new(omap_timer_fire, s);
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
- memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
"omap-mpu-timer", 0x100);
memory_region_add_subregion(system_memory, base, &s->iomem);
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
{
- qemu_del_timer(s->timer.timer);
+ timer_del(s->timer.timer);
if (!s->mode)
omap_clk_get(s->timer.clk);
s->mode = 1;
hwaddr base,
qemu_irq irq, omap_clk clk)
{
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
- g_malloc0(sizeof(struct omap_watchdog_timer_s));
+ struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
s->timer.irq = irq;
s->timer.clk = clk;
- s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
+ s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
- memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
"omap-wd-timer", 0x100);
memory_region_add_subregion(memory, base, &s->iomem);
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
- return omap_badwidth_write32(opaque, addr, value);
+ omap_badwidth_write32(opaque, addr, value);
+ return;
}
switch (offset) {
static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
{
- qemu_del_timer(s->timer.timer);
+ timer_del(s->timer.timer);
s->timer.enable = 0;
s->timer.it_ena = 0;
s->timer.reset_val = 0x00ffffff;
hwaddr base,
qemu_irq irq, omap_clk clk)
{
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
- g_malloc0(sizeof(struct omap_32khz_timer_s));
+ struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
s->timer.irq = irq;
s->timer.clk = clk;
- s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
+ s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
- memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
"omap-os-timer", 0x800);
memory_region_add_subregion(memory, base, &s->iomem);
uint16_t diff;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
- now = qemu_get_clock_ns(vm_clock);
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & 1)
s->ulpd_gauge_start = now;
now -= s->ulpd_gauge_start;
/* 32-kHz ticks */
- ticks = muldiv64(now, 32768, get_ticks_per_sec());
+ ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND);
s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_32K */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
/* High frequency ticks */
- ticks = muldiv64(now, 12000000, get_ticks_per_sec());
+ ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND);
s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_HI_FREQ */
hwaddr base,
struct omap_mpu_state_s *mpu)
{
- memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
+ memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
"omap-ulpd-pm", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
omap_ulpd_pm_reset(mpu);
uint32_t diff, uint32_t value)
{
if (s->compat1509) {
- if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
- omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
- (value >> 31) & 1);
- if (diff & (1 << 1)) /* CLK32K */
- omap_clk_onoff(omap_findclk(s, "clk32k_out"),
- (~value >> 1) & 1);
+ if (diff & (1U << 31)) {
+ /* MCBSP3_CLK_HIZ_DI */
+ omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
+ }
+ if (diff & (1 << 1)) {
+ /* CLK32K */
+ omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
+ }
}
}
static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
uint32_t diff, uint32_t value)
{
- if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
- omap_clk_reparent(omap_findclk(s, "uart3_ck"),
- omap_findclk(s, ((value >> 31) & 1) ?
- "ck_48m" : "armper_ck"));
+ if (diff & (1U << 31)) {
+ /* CONF_MOD_UART3_CLK_MODE_R */
+ omap_clk_reparent(omap_findclk(s, "uart3_ck"),
+ omap_findclk(s, ((value >> 31) & 1) ?
+ "ck_48m" : "armper_ck"));
+ }
if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
omap_clk_reparent(omap_findclk(s, "uart2_ck"),
omap_findclk(s, ((value >> 30) & 1) ?
uint32_t diff;
if (size != 4) {
- return omap_badwidth_write32(opaque, addr, value);
+ omap_badwidth_write32(opaque, addr, value);
+ return;
}
switch (addr) {
hwaddr base,
struct omap_mpu_state_s *mpu)
{
- memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
+ memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
"omap-pin-cfg", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
omap_pin_cfg_reset(mpu);
uint64_t value, unsigned size)
{
if (size != 4) {
- return omap_badwidth_write32(opaque, addr, value);
+ omap_badwidth_write32(opaque, addr, value);
+ return;
}
OMAP_BAD_REG(addr);
static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
{
- memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
+ memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
"omap-id", 0x100000000ULL);
- memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
+ memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
0xfffe1800, 0x800);
memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
- memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
+ memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
0xfffed400, 0x100);
memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
if (!cpu_is_omap15xx(mpu)) {
- memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
+ memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
&mpu->id_iomem, 0xfffe2000, 0x800);
memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
}
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
- return omap_badwidth_write32(opaque, addr, value);
+ omap_badwidth_write32(opaque, addr, value);
+ return;
}
switch (addr) {
static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
- memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
+ memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
"omap-mpui", 0x100);
memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
if (size < 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
- g_malloc0(sizeof(struct omap_tipb_bridge_s));
+ struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
- memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
"omap-tipb-bridge", 0x100);
memory_region_add_subregion(memory, base, &s->iomem);
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
- return omap_badwidth_write32(opaque, addr, value);
+ omap_badwidth_write32(opaque, addr, value);
+ return;
}
switch (addr) {
static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
- memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
+ memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
"omap-tcmi", 0x100);
memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
omap_tcmi_reset(mpu);
int div, mult;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
if (addr == 0x00) { /* CTL_REG */
hwaddr base, omap_clk clk)
{
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
- memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
+ memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
};
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
uint16_t diff;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (addr) {
static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
hwaddr dsp_base, struct omap_mpu_state_s *s)
{
- memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
+ memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
"omap-clkm", 0x100);
- memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
+ memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
"omap-clkdsp", 0x1000);
s->clkm.arm_idlect1 = 0x03ff;
int ln;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (offset) {
case 0x04: /* OUTPUT_REG */
diff = (s->outputs ^ value) & ~s->dir;
s->outputs = value;
- while ((ln = ffs(diff))) {
- ln --;
+ while ((ln = ctz32(diff)) != 32) {
if (s->handler[ln])
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
diff &= ~(1 << ln);
s->dir = value;
value = s->outputs & ~s->dir;
- while ((ln = ffs(diff))) {
- ln --;
+ while ((ln = ctz32(diff)) != 32) {
if (s->handler[ln])
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
diff &= ~(1 << ln);
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
- struct omap_mpuio_s *s = (struct omap_mpuio_s *)
- g_malloc0(sizeof(struct omap_mpuio_s));
+ struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
s->irq = gpio_int;
s->kbd_irq = kbd_int;
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
- memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
"omap-mpuio", 0x800);
memory_region_add_subregion(memory, base, &s->iomem);
- omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
+ omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0));
return s;
}
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
- return omap_badwidth_write16(opaque, addr, value);
+ omap_badwidth_write16(opaque, addr, value);
+ return;
}
switch (offset) {
qemu_irq dma,
omap_clk clk)
{
- struct omap_uwire_s *s = (struct omap_uwire_s *)
- g_malloc0(sizeof(struct omap_uwire_s));
+ struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
s->txirq = txirq;
s->rxirq = rxirq;
s->txdrq = dma;
omap_uwire_reset(s);
- memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800);
+ memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
- return omap_badwidth_write8(opaque, addr, value);
+ omap_badwidth_write8(opaque, addr, value);
+ return;
}
switch (offset) {
omap_pwl_reset(s);
- memory_region_init_io(&s->iomem, &omap_pwl_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
"omap-pwl", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
- omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
+ omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0));
return s;
}
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
- return omap_badwidth_write8(opaque, addr, value);
+ omap_badwidth_write8(opaque, addr, value);
+ return;
}
switch (offset) {
s->clk = clk;
omap_pwt_reset(s);
- memory_region_init_io(&s->iomem, &omap_pwt_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
"omap-pwt", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
time_t ti[2];
if (size != 1) {
- return omap_badwidth_write8(opaque, addr, value);
+ omap_badwidth_write8(opaque, addr, value);
+ return;
}
switch (offset) {
s->ti += ti[1];
} else {
/* A less accurate version */
- s->ti -= (s->current_tm.tm_year % 100) * 31536000;
- s->ti += from_bcd(value) * 31536000;
+ s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000;
+ s->ti += (time_t)from_bcd(value) * 31536000;
}
return;
if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
s->tick += s->comp_reg * 1000 / 32768;
- qemu_mod_timer(s->clk, s->tick);
+ timer_mod(s->clk, s->tick);
}
static void omap_rtc_reset(struct omap_rtc_s *s)
s->pm_am = 0;
s->auto_comp = 0;
s->round = 0;
- s->tick = qemu_get_clock_ms(rtc_clock);
+ s->tick = qemu_clock_get_ms(rtc_clock);
memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
s->alarm_tm.tm_mday = 0x01;
s->status = 1 << 7;
qemu_irq timerirq, qemu_irq alarmirq,
omap_clk clk)
{
- struct omap_rtc_s *s = (struct omap_rtc_s *)
- g_malloc0(sizeof(struct omap_rtc_s));
+ struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1);
s->irq = timerirq;
s->alarm = alarmirq;
- s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s);
+ s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
- memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
"omap-rtc", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
omap_mcbsp_rx_newdata(s);
- qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
- get_ticks_per_sec());
+ timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ NANOSECONDS_PER_SECOND);
}
static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
{
- qemu_del_timer(s->source_timer);
+ timer_del(s->source_timer);
}
static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
omap_mcbsp_tx_newdata(s);
- qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
- get_ticks_per_sec());
+ timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ NANOSECONDS_PER_SECOND);
}
static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
{
s->tx_req = 0;
omap_mcbsp_tx_done(s);
- qemu_del_timer(s->sink_timer);
+ timer_del(s->sink_timer);
}
static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
uint64_t value, unsigned size)
{
switch (size) {
- case 2: return omap_mcbsp_writeh(opaque, addr, value);
- case 4: return omap_mcbsp_writew(opaque, addr, value);
- default: return omap_badwidth_write16(opaque, addr, value);
+ case 2:
+ omap_mcbsp_writeh(opaque, addr, value);
+ break;
+ case 4:
+ omap_mcbsp_writew(opaque, addr, value);
+ break;
+ default:
+ omap_badwidth_write16(opaque, addr, value);
}
}
s->rx_req = 0;
s->tx_rate = 0;
s->rx_rate = 0;
- qemu_del_timer(s->source_timer);
- qemu_del_timer(s->sink_timer);
+ timer_del(s->source_timer);
+ timer_del(s->sink_timer);
}
static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq *dma, omap_clk clk)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
- g_malloc0(sizeof(struct omap_mcbsp_s));
+ struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1);
s->txirq = txirq;
s->rxirq = rxirq;
s->txdrq = dma[0];
s->rxdrq = dma[1];
- s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
- s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
+ s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s);
+ s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
- memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
+ memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
{
s->codec = slave;
- slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
- slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
+ slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0);
+ slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0);
}
/* LED Pulse Generators */
struct omap_lpg_s *s = opaque;
if (s->cycle)
- qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->period - s->on);
+ timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on);
else
- qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->on);
+ timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on);
s->cycle = !s->cycle;
printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
}
- qemu_del_timer(s->tm);
+ timer_del(s->tm);
if (on == period && s->on < s->period)
printf("%s: LED is on\n", __FUNCTION__);
else if (on == 0 && s->on)
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
- return omap_badwidth_write8(opaque, addr, value);
+ omap_badwidth_write8(opaque, addr, value);
+ return;
}
switch (offset) {
static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
hwaddr base, omap_clk clk)
{
- struct omap_lpg_s *s = (struct omap_lpg_s *)
- g_malloc0(sizeof(struct omap_lpg_s));
+ struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1);
- s->tm = qemu_new_timer_ms(vm_clock, omap_lpg_tick, s);
+ s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
omap_lpg_reset(s);
- memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
+ memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
- omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
+ omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0));
return s;
}
static void omap_setup_mpui_io(MemoryRegion *system_memory,
struct omap_mpu_state_s *mpu)
{
- memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
+ memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
"omap-mpui-io", 0x7fff);
memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
&mpu->mpui_io_iomem);
for (; map->phys_dsp; map ++) {
io = g_new(MemoryRegion, 1);
- memory_region_init_alias(io, map->name,
+ memory_region_init_alias(io, NULL, map->name,
system_memory, map->phys_mpu, map->size);
memory_region_add_subregion(system_memory, map->phys_dsp, io);
}
const char *core)
{
int i;
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
- g_malloc0(sizeof(struct omap_mpu_state_s));
- qemu_irq *cpu_irq;
+ struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
SysBusDevice *busdev;
s->sdram_size = sdram_size;
s->sram_size = OMAP15XX_SRAM_SIZE;
- s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
+ s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
/* Clocks */
omap_clk_init(s);
/* Memory-mapped stuff */
- memory_region_init_ram(&s->emiff_ram, "omap1.dram", s->sdram_size);
- vmstate_register_ram_global(&s->emiff_ram);
+ memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram",
+ s->sdram_size);
memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
- memory_region_init_ram(&s->imif_ram, "omap1.sram", s->sram_size);
+ memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
+ &error_fatal);
vmstate_register_ram_global(&s->imif_ram);
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
- cpu_irq = arm_pic_init_cpu(s->cpu);
s->ih[0] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
- sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
- sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
+ sysbus_connect_irq(busdev, 1,
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
sysbus_mmio_map(busdev, 0, 0xfffecb00);
s->ih[1] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[1], "size", 0x800);
fprintf(stderr, "qemu: missing SecureDigital device\n");
exit(1);
}
- s->mmc = omap_mmc_init(0xfffb7800, system_memory, dinfo->bdrv,
+ s->mmc = omap_mmc_init(0xfffb7800, system_memory,
+ blk_by_legacy_dinfo(dinfo),
qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
&s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
projects / qemu.git / blobdiff