qdev: set properties with device_class_set_props()

[qemu.git] / hw / char / parallel.c

diff --git a/hw/char/parallel.c b/hw/char/parallel.c
index 75a1a2f55e4927f27b194f3f71b42fb339d902d5..8dd67d13759b03e0eab8cbb9224567ad223963da 100644 (file)
--- a/hw/char/parallel.c
+++ b/hw/char/parallel.c
@@ -22,14 +22,20 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */

+

 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/osdep.h"
 #include "qapi/error.h"

-#include "hw/hw.h"
+#include "qemu/module.h"

 #include "chardev/char-parallel.h"
 #include "chardev/char-fe.h"
 #include "chardev/char-parallel.h"
 #include "chardev/char-fe.h"

+#include "hw/irq.h"

 #include "hw/isa/isa.h"
 #include "hw/isa/isa.h"

-#include "hw/i386/pc.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "hw/char/parallel.h"
+#include "sysemu/reset.h"

 #include "sysemu/sysemu.h"
 #include "sysemu/sysemu.h"

+#include "trace.h"

 
 //#define DEBUG_PARALLEL
 
 
 //#define DEBUG_PARALLEL
 


@@ -110,9 +116,8 @@ parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
 {
     ParallelState *s = opaque;
 
 {
     ParallelState *s = opaque;
 

-    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
-

     addr &= 7;
     addr &= 7;

+    trace_parallel_ioport_write("SW", addr, val);

     switch(addr) {
     case PARA_REG_DATA:
         s->dataw = val;
     switch(addr) {
     case PARA_REG_DATA:
         s->dataw = val;


@@ -157,6 +162,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
     s->last_read_offset = ~0U;
 
     addr &= 7;
     s->last_read_offset = ~0U;
 
     addr &= 7;

+    trace_parallel_ioport_write("HW", addr, val);

     switch(addr) {
     case PARA_REG_DATA:
         if (s->dataw == val)
     switch(addr) {
     case PARA_REG_DATA:
         if (s->dataw == val)


@@ -230,6 +236,8 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
     struct ParallelIOArg ioarg = {
         .buffer = &eppdata, .count = sizeof(eppdata)
     };
     struct ParallelIOArg ioarg = {
         .buffer = &eppdata, .count = sizeof(eppdata)
     };

+
+    trace_parallel_ioport_write("EPP", addr, val);

     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
         /* Controls not correct for EPP data cycle, so do nothing */
         pdebug("we%04x s\n", val);
     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
         /* Controls not correct for EPP data cycle, so do nothing */
         pdebug("we%04x s\n", val);


@@ -253,6 +261,8 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
     struct ParallelIOArg ioarg = {
         .buffer = &eppdata, .count = sizeof(eppdata)
     };
     struct ParallelIOArg ioarg = {
         .buffer = &eppdata, .count = sizeof(eppdata)
     };

+
+    trace_parallel_ioport_write("EPP", addr, val);

     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
         /* Controls not correct for EPP data cycle, so do nothing */
         pdebug("we%08x s\n", val);
     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
         /* Controls not correct for EPP data cycle, so do nothing */
         pdebug("we%08x s\n", val);


@@ -299,7 +309,7 @@ static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
         ret = s->control;
         break;
     }
         ret = s->control;
         break;
     }

-    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
+    trace_parallel_ioport_read("SW", addr, ret);

     return ret;
 }
 
     return ret;
 }
 


@@ -371,6 +381,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
         }
         break;
     }
         }
         break;
     }

+    trace_parallel_ioport_read("HW", addr, ret);

     s->last_read_offset = addr;
     return ret;
 }
     s->last_read_offset = addr;
     return ret;
 }


@@ -399,6 +410,7 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
     }
     else
         pdebug("re%04x\n", ret);
     }
     else
         pdebug("re%04x\n", ret);

+    trace_parallel_ioport_read("EPP", addr, ret);

     return ret;
 }
 
     return ret;
 }
 


@@ -426,11 +438,13 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
     }
     else
         pdebug("re%08x\n", ret);
     }
     else
         pdebug("re%08x\n", ret);

+    trace_parallel_ioport_read("EPP", addr, ret);

     return ret;
 }
 
 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
 {
     return ret;
 }
 
 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
 {

+    trace_parallel_ioport_write("ECP", addr & 7, val);

     pdebug("wecp%d=%02x\n", addr & 7, val);
 }
 
     pdebug("wecp%d=%02x\n", addr & 7, val);
 }
 


@@ -438,6 +452,7 @@ static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
 {
     uint8_t ret = 0xff;
 
 {
     uint8_t ret = 0xff;
 

+    trace_parallel_ioport_read("ECP", addr & 7, ret);

     pdebug("recp%d:%02x\n", addr & 7, ret);
     return ret;
 }
     pdebug("recp%d:%02x\n", addr & 7, ret);
     return ret;
 }


@@ -503,6 +518,10 @@ static const VMStateDescription vmstate_parallel_isa = {
     }
 };
 
     }
 };
 

+static int parallel_can_receive(void *opaque)
+{
+     return 1;
+}

 
 static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
 {
 
 static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
 {


@@ -513,7 +532,7 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
     int base;
     uint8_t dummy;
 
     int base;
     uint8_t dummy;
 

-    if (!qemu_chr_fe_get_driver(&s->chr)) {
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {

         error_setg(errp, "Can't create parallel device, empty char device");
         return;
     }
         error_setg(errp, "Can't create parallel device, empty char device");
         return;
     }


@@ -535,6 +554,8 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
     isa_init_irq(isadev, &s->irq, isa->isairq);
     qemu_register_reset(parallel_reset, s);
 
     isa_init_irq(isadev, &s->irq, isa->isairq);
     qemu_register_reset(parallel_reset, s);
 

+    qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL,
+                             NULL, NULL, s, NULL, true);

     if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
         s->hw_driver = 1;
         s->status = dummy;
     if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
         s->hw_driver = 1;
         s->status = dummy;


@@ -548,56 +569,28 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
 }
 
 /* Memory mapped interface */
 }
 
 /* Memory mapped interface */

-static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
-{
-    ParallelState *s = opaque;
-
-    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
-}
-
-static void parallel_mm_writeb (void *opaque,
-                                hwaddr addr, uint32_t value)
-{
-    ParallelState *s = opaque;
-
-    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
-}
-
-static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
-{
-    ParallelState *s = opaque;
-
-    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
-}
-
-static void parallel_mm_writew (void *opaque,
-                                hwaddr addr, uint32_t value)
-{
-    ParallelState *s = opaque;
-
-    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
-}
-
-static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
+static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size)

 {
     ParallelState *s = opaque;
 
 {
     ParallelState *s = opaque;
 

-    return parallel_ioport_read_sw(s, addr >> s->it_shift);
+    return parallel_ioport_read_sw(s, addr >> s->it_shift) &
+        MAKE_64BIT_MASK(0, size * 8);

 }
 
 }
 

-static void parallel_mm_writel (void *opaque,
-                                hwaddr addr, uint32_t value)
+static void parallel_mm_writefn(void *opaque, hwaddr addr,
+                                uint64_t value, unsigned size)

 {
     ParallelState *s = opaque;
 
 {
     ParallelState *s = opaque;
 

-    parallel_ioport_write_sw(s, addr >> s->it_shift, value);
+    parallel_ioport_write_sw(s, addr >> s->it_shift,
+                             value & MAKE_64BIT_MASK(0, size * 8));

 }
 
 static const MemoryRegionOps parallel_mm_ops = {
 }
 
 static const MemoryRegionOps parallel_mm_ops = {

-    .old_mmio = {
-        .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
-        .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
-    },
+    .read = parallel_mm_readfn,
+    .write = parallel_mm_writefn,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,

     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 


@@ -634,7 +627,7 @@ static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
 
     dc->realize = parallel_isa_realizefn;
     dc->vmsd = &vmstate_parallel_isa;
 
     dc->realize = parallel_isa_realizefn;
     dc->vmsd = &vmstate_parallel_isa;

-    dc->props = parallel_isa_properties;
+    device_class_set_props(dc, parallel_isa_properties);

     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 }
 
     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 }