return 0;
}
- iobase = object_property_get_int(obj, "iobase", &local_err);
+ iobase = object_property_get_uint(obj, "iobase", &local_err);
if (local_err || iobase != 0x3f0) {
error_free(local_err);
return 0;
}
if (state.multiple) {
- error_report("warning: multiple floppy disk controllers with "
- "iobase=0x3f0 have been found");
+ warn_report("multiple floppy disk controllers with "
+ "iobase=0x3f0 have been found");
error_printf("the one being picked for CMOS setup might not reflect "
- "your intent\n");
+ "your intent");
}
return state.floppy;
cpu = object_new(typename);
- object_property_set_int(cpu, apic_id, "apic-id", &local_err);
+ object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
object_property_set_bool(cpu, true, "realized", &local_err);
object_unref(cpu);
void pc_hot_add_cpu(const int64_t id, Error **errp)
{
- ObjectClass *oc;
MachineState *ms = MACHINE(qdev_get_machine());
int64_t apic_id = x86_cpu_apic_id_from_index(id);
Error *local_err = NULL;
return;
}
- assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */
- oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu));
- pc_new_cpu(object_class_get_name(oc), apic_id, &local_err);
+ pc_new_cpu(ms->cpu_type, apic_id, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
void pc_cpus_init(PCMachineState *pcms)
{
int i;
- CPUClass *cc;
- ObjectClass *oc;
- const char *typename;
- gchar **model_pieces;
const CPUArchIdList *possible_cpus;
- MachineState *machine = MACHINE(pcms);
+ MachineState *ms = MACHINE(pcms);
MachineClass *mc = MACHINE_GET_CLASS(pcms);
- /* init CPUs */
- if (machine->cpu_model == NULL) {
-#ifdef TARGET_X86_64
- machine->cpu_model = "qemu64";
-#else
- machine->cpu_model = "qemu32";
-#endif
- }
-
- model_pieces = g_strsplit(machine->cpu_model, ",", 2);
- if (!model_pieces[0]) {
- error_report("Invalid/empty CPU model name");
- exit(1);
- }
-
- oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]);
- if (oc == NULL) {
- error_report("Unable to find CPU definition: %s", model_pieces[0]);
- exit(1);
- }
- typename = object_class_get_name(oc);
- cc = CPU_CLASS(oc);
- cc->parse_features(typename, model_pieces[1], &error_fatal);
- g_strfreev(model_pieces);
-
/* Calculates the limit to CPU APIC ID values
*
* Limit for the APIC ID value, so that all
* This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
*/
pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
- possible_cpus = mc->possible_cpu_arch_ids(machine);
+ possible_cpus = mc->possible_cpu_arch_ids(ms);
for (i = 0; i < smp_cpus; i++) {
- pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal);
+ pc_new_cpu(ms->cpu_type, possible_cpus->cpus[i].arch_id, &error_fatal);
}
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
if (filename == NULL) {
- fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
+ warn_report("failed to find %s", default_dsdt);
} else {
QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
&error_abort);
acpi_table_add_builtin(opts, &err);
if (err) {
- error_reportf_err(err, "WARNING: failed to load %s: ",
- filename);
+ warn_reportf_err(err, "failed to load %s: ", filename);
}
g_free(filename);
}
option_rom_mr = g_malloc(sizeof(*option_rom_mr));
memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
&error_fatal);
- vmstate_register_ram_global(option_rom_mr);
+ if (pcmc->pci_enabled) {
+ memory_region_set_readonly(option_rom_mr, true);
+ }
memory_region_add_subregion_overlap(rom_memory,
PC_ROM_MIN_VGA,
option_rom_mr,
* and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
* IRQ8 and IRQ2.
*/
- uint8_t compat = object_property_get_int(OBJECT(hpet),
+ uint8_t compat = object_property_get_uint(OBJECT(hpet),
HPET_INTCAP, NULL);
if (!compat) {
qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
PCDIMMDevice *dimm = PC_DIMM(dev);
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
- MemoryRegion *mr = ddc->get_memory_region(dimm);
+ MemoryRegion *mr;
uint64_t align = TARGET_PAGE_SIZE;
+ bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
+
+ mr = ddc->get_memory_region(dimm, &local_err);
+ if (local_err) {
+ goto out;
+ }
if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {
align = memory_region_get_alignment(mr);
goto out;
}
+ if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
+ error_setg(&local_err,
+ "nvdimm is not enabled: missing 'nvdimm' in '-M'");
+ goto out;
+ }
+
pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);
if (local_err) {
goto out;
}
- if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
- if (!pcms->acpi_nvdimm_state.is_enabled) {
- error_setg(&local_err,
- "nvdimm is not enabled: missing 'nvdimm' in '-M'");
- goto out;
- }
+ if (is_nvdimm) {
nvdimm_plug(&pcms->acpi_nvdimm_state);
}
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
PCDIMMDevice *dimm = PC_DIMM(dev);
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
- MemoryRegion *mr = ddc->get_memory_region(dimm);
+ MemoryRegion *mr;
HotplugHandlerClass *hhc;
Error *local_err = NULL;
+ mr = ddc->get_memory_region(dimm, &local_err);
+ if (local_err) {
+ goto out;
+ }
+
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
CPUArchId *cpu_slot;
X86CPUTopoInfo topo;
X86CPU *cpu = X86_CPU(dev);
+ MachineState *ms = MACHINE(hotplug_dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
+ if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
+ error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
+ ms->cpu_type);
+ return;
+ }
+
/* if APIC ID is not set, set it based on socket/core/thread properties */
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
}
if (value < (1ULL << 20)) {
- error_report("Warning: small max_ram_below_4g(%"PRIu64
- ") less than 1M. BIOS may not work..",
- value);
+ warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
+ "BIOS may not work with less than 1MiB", value);
}
pcms->max_ram_below_4g = value;
return possible_cpus->cpus[cpu_index].props;
}
+static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
+{
+ X86CPUTopoInfo topo;
+
+ assert(idx < ms->possible_cpus->len);
+ x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
+ smp_cores, smp_threads, &topo);
+ return topo.pkg_id % nb_numa_nodes;
+}
+
static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
{
int i;
ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
ms->possible_cpus->cpus[i].props.has_thread_id = true;
ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
-
- /* default distribution of CPUs over NUMA nodes */
- if (nb_numa_nodes) {
- /* preset values but do not enable them i.e. 'has_node_id = false',
- * numa init code will enable them later if manual mapping wasn't
- * present on CLI */
- ms->possible_cpus->cpus[i].props.node_id =
- topo.pkg_id % nb_numa_nodes;
- }
}
return ms->possible_cpus;
}
pcmc->linuxboot_dma_enabled = true;
mc->get_hotplug_handler = pc_get_hotpug_handler;
mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
+ mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
mc->has_hotpluggable_cpus = true;
mc->default_boot_order = "cad";
hc->unplug_request = pc_machine_device_unplug_request_cb;
hc->unplug = pc_machine_device_unplug_cb;
nc->nmi_monitor_handler = x86_nmi;
+ mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int",
pc_machine_get_hotplug_memory_region_size, NULL,
projects / qemu.git / blobdiff