static bool ahci_pedantic;
/*** Function Declarations ***/
-static QPCIDevice *get_ahci_device(uint32_t *fingerprint);
-static void start_ahci_device(AHCIQState *ahci);
-static void free_ahci_device(QPCIDevice *dev);
-
static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
static void ahci_test_pci_spec(AHCIQState *ahci);
static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
}
}
-static uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
-{
- return qmalloc(ahci->parent, bytes);
-}
-
-/**
- * Locate, verify, and return a handle to the AHCI device.
- */
-static QPCIDevice *get_ahci_device(uint32_t *fingerprint)
-{
- QPCIDevice *ahci;
- uint32_t ahci_fingerprint;
- QPCIBus *pcibus;
-
- pcibus = qpci_init_pc();
-
- /* Find the AHCI PCI device and verify it's the right one. */
- ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
- g_assert(ahci != NULL);
-
- ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
-
- switch (ahci_fingerprint) {
- case AHCI_INTEL_ICH9:
- break;
- default:
- /* Unknown device. */
- g_assert_not_reached();
- }
-
- if (fingerprint) {
- *fingerprint = ahci_fingerprint;
- }
- return ahci;
-}
-
-static void free_ahci_device(QPCIDevice *dev)
-{
- QPCIBus *pcibus = dev ? dev->bus : NULL;
-
- /* libqos doesn't have a function for this, so free it manually */
- g_free(dev);
- qpci_free_pc(pcibus);
-}
-
/*** Test Setup & Teardown ***/
/**
"-device ide-hd,drive=drive0 "
"-global ide-hd.ver=%s";
s->parent = qtest_pc_boot(cli, tmp_path, "testdisk", "version");
+ alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
/* Verify that we have an AHCI device present. */
s->dev = get_ahci_device(&s->fingerprint);
static void ahci_shutdown(AHCIQState *ahci)
{
QOSState *qs = ahci->parent;
+
+ ahci_clean_mem(ahci);
free_ahci_device(ahci->dev);
g_free(ahci);
qtest_shutdown(qs);
}
-/*** Logical Device Initialization ***/
-
-/**
- * Start the PCI device and sanity-check default operation.
- */
-static void ahci_pci_enable(AHCIQState *ahci)
-{
- uint8_t reg;
-
- start_ahci_device(ahci);
-
- switch (ahci->fingerprint) {
- case AHCI_INTEL_ICH9:
- /* ICH9 has a register at PCI 0x92 that
- * acts as a master port enabler mask. */
- reg = qpci_config_readb(ahci->dev, 0x92);
- reg |= 0x3F;
- qpci_config_writeb(ahci->dev, 0x92, reg);
- /* 0...0111111b -- bit significant, ports 0-5 enabled. */
- ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
- break;
- }
-
-}
-
-/**
- * Map BAR5/ABAR, and engage the PCI device.
- */
-static void start_ahci_device(AHCIQState *ahci)
-{
- /* Map AHCI's ABAR (BAR5) */
- ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
-
- /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
- qpci_device_enable(ahci->dev);
-}
-
-/**
- * Test and initialize the AHCI's HBA memory areas.
- * Initialize and start any ports with devices attached.
- * Bring the HBA into the idle state.
- */
-static void ahci_hba_enable(AHCIQState *ahci)
-{
- /* Bits of interest in this section:
- * GHC.AE Global Host Control / AHCI Enable
- * PxCMD.ST Port Command: Start
- * PxCMD.SUD "Spin Up Device"
- * PxCMD.POD "Power On Device"
- * PxCMD.FRE "FIS Receive Enable"
- * PxCMD.FR "FIS Receive Running"
- * PxCMD.CR "Command List Running"
- */
- uint32_t reg, ports_impl;
- uint16_t i;
- uint8_t num_cmd_slots;
-
- g_assert(ahci != NULL);
-
- /* Set GHC.AE to 1 */
- ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
- reg = ahci_rreg(ahci, AHCI_GHC);
- ASSERT_BIT_SET(reg, AHCI_GHC_AE);
-
- /* Cache CAP and CAP2. */
- ahci->cap = ahci_rreg(ahci, AHCI_CAP);
- ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
-
- /* Read CAP.NCS, how many command slots do we have? */
- num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
- g_test_message("Number of Command Slots: %u", num_cmd_slots);
-
- /* Determine which ports are implemented. */
- ports_impl = ahci_rreg(ahci, AHCI_PI);
-
- for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
- if (!(ports_impl & 0x01)) {
- continue;
- }
-
- g_test_message("Initializing port %u", i);
-
- reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
- if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
- AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
- g_test_message("port is idle");
- } else {
- g_test_message("port needs to be idled");
- ahci_px_clr(ahci, i, AHCI_PX_CMD,
- (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
- /* The port has 500ms to disengage. */
- usleep(500000);
- reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
- ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
- ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
- g_test_message("port is now idle");
- /* The spec does allow for possibly needing a PORT RESET
- * or HBA reset if we fail to idle the port. */
- }
-
- /* Allocate Memory for the Command List Buffer & FIS Buffer */
- /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
- ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
- qmemset(ahci->port[i].clb, 0x00, 0x100);
- g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
- ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
- g_assert_cmphex(ahci->port[i].clb, ==,
- ahci_px_rreg(ahci, i, AHCI_PX_CLB));
-
- /* PxFB space ... 0x100, as in 4.2.1 p 35 */
- ahci->port[i].fb = ahci_alloc(ahci, 0x100);
- qmemset(ahci->port[i].fb, 0x00, 0x100);
- g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
- ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
- g_assert_cmphex(ahci->port[i].fb, ==,
- ahci_px_rreg(ahci, i, AHCI_PX_FB));
-
- /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
- ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
- ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
- ahci_wreg(ahci, AHCI_IS, (1 << i));
-
- /* Verify Interrupts Cleared */
- reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
- g_assert_cmphex(reg, ==, 0);
-
- reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
- g_assert_cmphex(reg, ==, 0);
-
- reg = ahci_rreg(ahci, AHCI_IS);
- ASSERT_BIT_CLEAR(reg, (1 << i));
-
- /* Enable All Interrupts: */
- ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
- reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
- g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
-
- /* Enable the FIS Receive Engine. */
- ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
- reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
- ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
-
- /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
- * physical presence, a device is present and may be started. However,
- * PxSERR.DIAG.X /may/ need to be cleared a priori. */
- reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
- if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
- ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
- }
-
- reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
- if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
- reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
- if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
- /* Device Found: set PxCMD.ST := 1 */
- ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
- ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
- AHCI_PX_CMD_CR);
- g_test_message("Started Device %u", i);
- } else if ((reg & AHCI_PX_SSTS_DET)) {
- /* Device present, but in some unknown state. */
- g_assert_not_reached();
- }
- }
- }
-
- /* Enable GHC.IE */
- ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
- reg = ahci_rreg(ahci, AHCI_GHC);
- ASSERT_BIT_SET(reg, AHCI_GHC_IE);
-
- /* TODO: The device should now be idling and waiting for commands.
- * In the future, a small test-case to inspect the Register D2H FIS
- * and clear the initial interrupts might be good. */
-}
-
/*** Specification Adherence Tests ***/
/**
*/
static void ahci_test_identify(AHCIQState *ahci)
{
- RegD2HFIS *d2h = g_malloc0(0x20);
- RegD2HFIS *pio = g_malloc0(0x20);
- RegH2DFIS fis;
- AHCICommand cmd;
- PRD prd;
- uint32_t ports, reg, table, data_ptr;
uint16_t buff[256];
- unsigned i;
+ unsigned px;
int rc;
+ uint16_t sect_size;
+ const size_t buffsize = 512;
g_assert(ahci != NULL);
- /* We need to:
- * (1) Create a Command Table Buffer and update the Command List Slot #0
- * to point to this buffer.
- * (2) Construct an FIS host-to-device command structure, and write it to
- * the top of the command table buffer.
- * (3) Create a data buffer for the IDENTIFY response to be sent to
- * (4) Create a Physical Region Descriptor that points to the data buffer,
- * and write it to the bottom (offset 0x80) of the command table.
- * (5) Now, PxCLB points to the command list, command 0 points to
- * our table, and our table contains an FIS instruction and a
- * PRD that points to our rx buffer.
- * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
+ /**
+ * This serves as a bit of a tutorial on AHCI device programming:
+ *
+ * (1) Create a data buffer for the IDENTIFY response to be sent to
+ * (2) Create a Command Table buffer, where we will store the
+ * command and PRDT (Physical Region Descriptor Table)
+ * (3) Construct an FIS host-to-device command structure, and write it to
+ * the top of the Command Table buffer.
+ * (4) Create one or more Physical Region Descriptors (PRDs) that describe
+ * a location in memory where data may be stored/retrieved.
+ * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
+ * (6) Each AHCI port has up to 32 command slots. Each slot contains a
+ * header that points to a Command Table buffer. Pick an unused slot
+ * and update it to point to the Command Table we have built.
+ * (7) Now: Command #n points to our Command Table, and our Command Table
+ * contains the FIS (that describes our command) and the PRDTL, which
+ * describes our buffer.
+ * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
+ * #n is ready for processing.
*/
/* Pick the first implemented and running port */
- ports = ahci_rreg(ahci, AHCI_PI);
- for (i = 0; i < 32; ports >>= 1, ++i) {
- if (ports == 0) {
- i = 32;
- }
-
- if (!(ports & 0x01)) {
- continue;
- }
+ px = ahci_port_select(ahci);
+ g_test_message("Selected port %u for test", px);
- reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
- if (BITSET(reg, AHCI_PX_CMD_ST)) {
- break;
- }
- }
- g_assert_cmphex(i, <, 32);
- g_test_message("Selected port %u for test", i);
-
- /* Clear out this port's interrupts (ignore the init register d2h fis) */
- reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
- ahci_px_wreg(ahci, i, AHCI_PX_IS, reg);
- g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
-
- /* Wipe the FIS-Receive Buffer */
- qmemset(ahci->port[i].fb, 0x00, 0x100);
-
- /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
- /* We need at least one PRD, so round up to the nearest 0x80 multiple. */
- table = ahci_alloc(ahci, CMD_TBL_SIZ(1));
- g_assert(table);
- ASSERT_BIT_CLEAR(table, 0x7F);
-
- /* Create a data buffer ... where we will dump the IDENTIFY data to. */
- data_ptr = ahci_alloc(ahci, 512);
- g_assert(data_ptr);
-
- /* Copy the existing Command #0 structure from the CLB into local memory,
- * and build a new command #0. */
- memread(ahci->port[i].clb, &cmd, sizeof(cmd));
- cmd.b1 = 5; /* reg_h2d_fis is 5 double-words long */
- cmd.b2 = 0x04; /* clear PxTFD.STS.BSY when done */
- cmd.prdtl = cpu_to_le16(1); /* One PRD table entry. */
- cmd.prdbc = 0;
- cmd.ctba = cpu_to_le32(table);
- cmd.ctbau = 0;
-
- /* Construct our PRD, noting that DBC is 0-indexed. */
- prd.dba = cpu_to_le32(data_ptr);
- prd.dbau = 0;
- prd.res = 0;
- /* 511+1 bytes, request DPS interrupt */
- prd.dbc = cpu_to_le32(511 | 0x80000000);
-
- /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
- memset(&fis, 0x00, sizeof(fis));
- fis.fis_type = 0x27; /* Register Host-to-Device FIS */
- fis.command = 0xEC; /* IDENTIFY */
- fis.device = 0;
- fis.flags = 0x80; /* Indicate this is a command FIS */
-
- /* We've committed nothing yet, no interrupts should be posted yet. */
- g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
-
- /* Commit the Command FIS to the Command Table */
- memwrite(table, &fis, sizeof(fis));
-
- /* Commit the PRD entry to the Command Table */
- memwrite(table + 0x80, &prd, sizeof(prd));
-
- /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
- memwrite(ahci->port[i].clb, &cmd, sizeof(cmd));
-
- /* Everything is in place, but we haven't given the go-ahead yet. */
- g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
-
- /* Issue Command #0 via PxCI */
- ahci_px_wreg(ahci, i, AHCI_PX_CI, (1 << 0));
- while (BITSET(ahci_px_rreg(ahci, i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
- usleep(50);
- }
+ /* Clear out the FIS Receive area and any pending interrupts. */
+ ahci_port_clear(ahci, px);
- /* Check for expected interrupts */
- reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
- ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS);
- ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS);
- /* BUG: we expect AHCI_PX_IS_DPS to be set. */
- ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS);
-
- /* Clear expected interrupts and assert all interrupts now cleared. */
- ahci_px_wreg(ahci, i, AHCI_PX_IS,
- AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
- g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
-
- /* Check for errors. */
- reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
- g_assert_cmphex(reg, ==, 0);
- reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
- ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
- ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
-
- /* Investigate CMD #0, assert that we read 512 bytes */
- memread(ahci->port[i].clb, &cmd, sizeof(cmd));
- g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc));
-
- /* Investigate FIS responses */
- memread(ahci->port[i].fb + 0x20, pio, 0x20);
- memread(ahci->port[i].fb + 0x40, d2h, 0x20);
- g_assert_cmphex(pio->fis_type, ==, 0x5f);
- g_assert_cmphex(d2h->fis_type, ==, 0x34);
- g_assert_cmphex(pio->flags, ==, d2h->flags);
- g_assert_cmphex(pio->status, ==, d2h->status);
- g_assert_cmphex(pio->error, ==, d2h->error);
-
- reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
- g_assert_cmphex((reg & AHCI_PX_TFD_ERR), ==, pio->error);
- g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, pio->status);
- /* The PIO Setup FIS contains a "bytes read" field, which is a
- * 16-bit value. The Physical Region Descriptor Byte Count is
- * 32-bit, but for small transfers using one PRD, it should match. */
- g_assert_cmphex(le16_to_cpu(pio->res4), ==, le32_to_cpu(cmd.prdbc));
-
- /* Last, but not least: Investigate the IDENTIFY response data. */
- memread(data_ptr, &buff, 512);
+ /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
+ ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize);
/* Check serial number/version in the buffer */
/* NB: IDENTIFY strings are packed in 16bit little endian chunks.
rc = memcmp(&buff[23], "version ", 8);
g_assert_cmphex(rc, ==, 0);
- g_free(d2h);
- g_free(pio);
+ sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
+ g_assert_cmphex(sect_size, ==, 0x200);
+}
+
+static void ahci_test_dma_rw_simple(AHCIQState *ahci)
+{
+ uint64_t ptr;
+ uint8_t port;
+ unsigned i;
+ const unsigned bufsize = 4096;
+ unsigned char *tx = g_malloc(bufsize);
+ unsigned char *rx = g_malloc0(bufsize);
+
+ g_assert(ahci != NULL);
+
+ /* Pick the first running port and clear it. */
+ port = ahci_port_select(ahci);
+ ahci_port_clear(ahci, port);
+
+ /*** Create pattern and transfer to guest ***/
+ /* Data buffer in the guest */
+ ptr = ahci_alloc(ahci, bufsize);
+ g_assert(ptr);
+
+ /* Write some indicative pattern to our 4K buffer. */
+ for (i = 0; i < bufsize; i++) {
+ tx[i] = (bufsize - i);
+ }
+ memwrite(ptr, tx, bufsize);
+
+ /* Write this buffer to disk, then read it back to the DMA buffer. */
+ ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize);
+ qmemset(ptr, 0x00, bufsize);
+ ahci_guest_io(ahci, port, CMD_READ_DMA, ptr, bufsize);
+
+ /*** Read back the Data ***/
+ memread(ptr, rx, bufsize);
+ g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
+
+ ahci_free(ahci, ptr);
+ g_free(tx);
+ g_free(rx);
}
/******************************************************************************/
ahci_shutdown(ahci);
}
+/**
+ * Perform a simple DMA R/W test, using a single PRD and non-NCQ commands.
+ */
+static void test_dma_rw_simple(void)
+{
+ AHCIQState *ahci;
+
+ ahci = ahci_boot();
+ ahci_pci_enable(ahci);
+ ahci_hba_enable(ahci);
+ ahci_test_dma_rw_simple(ahci);
+ ahci_shutdown(ahci);
+}
+
/******************************************************************************/
int main(int argc, char **argv)
qtest_add_func("/ahci/hba_spec", test_hba_spec);
qtest_add_func("/ahci/hba_enable", test_hba_enable);
qtest_add_func("/ahci/identify", test_identify);
+ qtest_add_func("/ahci/dma/simple", test_dma_rw_simple);
ret = g_test_run();
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