PPC: Fix dma interrupt

[qemu.git] / hw / apb_pci.c

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 163822617bc878699e338ee8dba888c6e6d1a22b..7eb0c2bbcb7e68bf8845efa7e28f8a41e52b43c8 100644 (file)
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -27,14 +27,13 @@
    the secondary PCI bridge.  */
 
 #include "sysbus.h"
    the secondary PCI bridge.  */
 
 #include "sysbus.h"

-#include "pci.h"
-#include "pci_host.h"
-#include "pci_bridge.h"
-#include "pci_internals.h"
-#include "rwhandler.h"
+#include "pci/pci.h"
+#include "pci/pci_host.h"
+#include "pci/pci_bridge.h"
+#include "pci/pci_bus.h"

 #include "apb_pci.h"
 #include "apb_pci.h"

-#include "sysemu.h"
-#include "exec-memory.h"
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"

 
 /* debug APB */
 //#define DEBUG_APB
 
 /* debug APB */
 //#define DEBUG_APB


@@ -67,25 +66,33 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
 #define RESET_WCMASK 0x98000000
 #define RESET_WMASK  0x60000000
 
 #define RESET_WCMASK 0x98000000
 #define RESET_WMASK  0x60000000
 

+#define MAX_IVEC 0x30
+

 typedef struct APBState {
     SysBusDevice busdev;
     PCIBus      *bus;
 typedef struct APBState {
     SysBusDevice busdev;
     PCIBus      *bus;

-    ReadWriteHandler pci_config_handler;
+    MemoryRegion apb_config;
+    MemoryRegion pci_config;
+    MemoryRegion pci_mmio;
+    MemoryRegion pci_ioport;

     uint32_t iommu[4];
     uint32_t pci_control[16];
     uint32_t pci_irq_map[8];
     uint32_t obio_irq_map[32];
     uint32_t iommu[4];
     uint32_t pci_control[16];
     uint32_t pci_irq_map[8];
     uint32_t obio_irq_map[32];

-    qemu_irq pci_irqs[32];
+    qemu_irq *pbm_irqs;
+    qemu_irq *ivec_irqs;

     uint32_t reset_control;
     unsigned int nr_resets;
 } APBState;
 
     uint32_t reset_control;
     unsigned int nr_resets;
 } APBState;
 

-static void apb_config_writel (void *opaque, target_phys_addr_t addr,
-                               uint32_t val)
+static void pci_apb_set_irq(void *opaque, int irq_num, int level);
+
+static void apb_config_writel (void *opaque, hwaddr addr,
+                               uint64_t val, unsigned size)

 {
     APBState *s = opaque;
 
 {
     APBState *s = opaque;
 

-    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
+    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);

 
     switch (addr & 0xffff) {
     case 0x30 ... 0x4f: /* DMA error registers */
 
     switch (addr & 0xffff) {
     case 0x30 ... 0x4f: /* DMA error registers */


@@ -102,6 +109,22 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
             s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
         }
         break;
             s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
         }
         break;

+    case 0x1000 ... 0x1080: /* OBIO interrupt control */
+        if (addr & 4) {
+            s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK;
+            s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
+        }
+        break;
+    case 0x1400 ... 0x143f: /* PCI interrupt clear */
+        if (addr & 4) {
+            pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
+        }
+        break;
+    case 0x1800 ... 0x1860: /* OBIO interrupt clear */
+        if (addr & 4) {
+            pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
+        }
+        break;

     case 0x2000 ... 0x202f: /* PCI control */
         s->pci_control[(addr & 0x3f) >> 2] = val;
         break;
     case 0x2000 ... 0x202f: /* PCI control */
         s->pci_control[(addr & 0x3f) >> 2] = val;
         break;


@@ -128,8 +151,8 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
     }
 }
 
     }
 }
 

-static uint32_t apb_config_readl (void *opaque,
-                                  target_phys_addr_t addr)
+static uint64_t apb_config_readl (void *opaque,
+                                  hwaddr addr, unsigned size)

 {
     APBState *s = opaque;
     uint32_t val;
 {
     APBState *s = opaque;
     uint32_t val;


@@ -152,6 +175,13 @@ static uint32_t apb_config_readl (void *opaque,
             val = 0;
         }
         break;
             val = 0;
         }
         break;

+    case 0x1000 ... 0x1080: /* OBIO interrupt control */
+        if (addr & 4) {
+            val = s->obio_irq_map[(addr & 0xff) >> 3];
+        } else {
+            val = 0;
+        }
+        break;

     case 0x2000 ... 0x202f: /* PCI control */
         val = s->pci_control[(addr & 0x3f) >> 2];
         break;
     case 0x2000 ... 0x202f: /* PCI control */
         val = s->pci_control[(addr & 0x3f) >> 2];
         break;


@@ -176,33 +206,27 @@ static uint32_t apb_config_readl (void *opaque,
     return val;
 }
 
     return val;
 }
 

-static CPUWriteMemoryFunc * const apb_config_write[] = {
-    &apb_config_writel,
-    &apb_config_writel,
-    &apb_config_writel,
-};
-
-static CPUReadMemoryFunc * const apb_config_read[] = {
-    &apb_config_readl,
-    &apb_config_readl,
-    &apb_config_readl,
+static const MemoryRegionOps apb_config_ops = {
+    .read = apb_config_readl,
+    .write = apb_config_writel,
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 };
 

-static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
-                                 uint32_t val, int size)
+static void apb_pci_config_write(void *opaque, hwaddr addr,
+                                 uint64_t val, unsigned size)

 {
 {

-    APBState *s = container_of(h, APBState, pci_config_handler);
+    APBState *s = opaque;

 
     val = qemu_bswap_len(val, size);
 
     val = qemu_bswap_len(val, size);

-    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
+    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);

     pci_data_write(s->bus, addr, val, size);
 }
 
     pci_data_write(s->bus, addr, val, size);
 }
 

-static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
-                                    int size)
+static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
+                                    unsigned size)

 {
     uint32_t ret;
 {
     uint32_t ret;

-    APBState *s = container_of(h, APBState, pci_config_handler);
+    APBState *s = opaque;

 
     ret = pci_data_read(s->bus, addr, size);
     ret = qemu_bswap_len(ret, size);
 
     ret = pci_data_read(s->bus, addr, size);
     ret = qemu_bswap_len(ret, size);


@@ -210,25 +234,25 @@ static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
     return ret;
 }
 
     return ret;
 }
 

-static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowriteb (void *opaque, hwaddr addr,

                                   uint32_t val)
 {
     cpu_outb(addr & IOPORTS_MASK, val);
 }
 
                                   uint32_t val)
 {
     cpu_outb(addr & IOPORTS_MASK, val);
 }
 

-static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritew (void *opaque, hwaddr addr,

                                   uint32_t val)
 {
     cpu_outw(addr & IOPORTS_MASK, bswap16(val));
 }
 
                                   uint32_t val)
 {
     cpu_outw(addr & IOPORTS_MASK, bswap16(val));
 }
 

-static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritel (void *opaque, hwaddr addr,

                                 uint32_t val)
 {
     cpu_outl(addr & IOPORTS_MASK, bswap32(val));
 }
 
                                 uint32_t val)
 {
     cpu_outl(addr & IOPORTS_MASK, bswap32(val));
 }
 

-static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)

 {
     uint32_t val;
 
 {
     uint32_t val;
 


@@ -236,7 +260,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
     return val;
 }
 
     return val;
 }
 

-static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)

 {
     uint32_t val;
 
 {
     uint32_t val;
 


@@ -244,7 +268,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
     return val;
 }
 
     return val;
 }
 

-static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)

 {
     uint32_t val;
 
 {
     uint32_t val;
 


@@ -252,16 +276,12 @@ static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
     return val;
 }
 
     return val;
 }
 

-static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
-    &pci_apb_iowriteb,
-    &pci_apb_iowritew,
-    &pci_apb_iowritel,
-};
-
-static CPUReadMemoryFunc * const pci_apb_ioread[] = {
-    &pci_apb_ioreadb,
-    &pci_apb_ioreadw,
-    &pci_apb_ioreadl,
+static const MemoryRegionOps pci_ioport_ops = {
+    .old_mmio = {
+        .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
+        .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
+    },
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 };
 
 /* The APB host has an IRQ line for each IRQ line of each slot.  */


@@ -288,10 +308,19 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
     if (irq_num < 32) {
         if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
     if (irq_num < 32) {
         if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);

-            qemu_set_irq(s->pci_irqs[irq_num], level);
+            qemu_set_irq(s->ivec_irqs[irq_num], level);
+        } else {
+            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
+            qemu_irq_lower(s->ivec_irqs[irq_num]);
+        }
+    } else {
+        /* OBIO IRQ map onto the next 16 INO.  */
+        if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) {
+            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
+            qemu_set_irq(s->ivec_irqs[irq_num], level);

         } else {
             APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
         } else {
             APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);

-            qemu_irq_lower(s->pci_irqs[irq_num]);
+            qemu_irq_lower(s->ivec_irqs[irq_num]);

         }
     }
 }
         }
     }
 }


@@ -322,21 +351,21 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
     return 0;
 }
 
     return 0;
 }
 

-PCIBus *pci_apb_init(target_phys_addr_t special_base,
-                     target_phys_addr_t mem_base,
-                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
+PCIBus *pci_apb_init(hwaddr special_base,
+                     hwaddr mem_base,
+                     qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
+                     qemu_irq **pbm_irqs)

 {
     DeviceState *dev;
     SysBusDevice *s;
     APBState *d;
 {
     DeviceState *dev;
     SysBusDevice *s;
     APBState *d;

-    unsigned int i;

     PCIDevice *pci_dev;
     PCIBridge *br;
 
     /* Ultrasparc PBM main bus */
     dev = qdev_create(NULL, "pbm");
     qdev_init_nofail(dev);
     PCIDevice *pci_dev;
     PCIBridge *br;
 
     /* Ultrasparc PBM main bus */
     dev = qdev_create(NULL, "pbm");
     qdev_init_nofail(dev);

-    s = sysbus_from_qdev(dev);
+    s = SYS_BUS_DEVICE(dev);

     /* apb_config */
     sysbus_mmio_map(s, 0, special_base);
     /* PCI configuration space */
     /* apb_config */
     sysbus_mmio_map(s, 0, special_base);
     /* PCI configuration space */


@@ -345,18 +374,19 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
     d = FROM_SYSBUS(APBState, s);
 
     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
     d = FROM_SYSBUS(APBState, s);
 

+    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
+    memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
+

     d->bus = pci_register_bus(&d->busdev.qdev, "pci",
     d->bus = pci_register_bus(&d->busdev.qdev, "pci",

-                                         pci_apb_set_irq, pci_pbm_map_irq, d,
-                                         get_system_memory(),
-                                         get_system_io(),
-                                         0, 32);
-    pci_bus_set_mem_base(d->bus, mem_base);
+                              pci_apb_set_irq, pci_pbm_map_irq, d,
+                              &d->pci_mmio,
+                              get_system_io(),
+                              0, 32);

 
 

-    for (i = 0; i < 32; i++) {
-        sysbus_connect_irq(s, i, pic[i]);
-    }
+    *pbm_irqs = d->pbm_irqs;
+    d->ivec_irqs = ivec_irqs;

 
 

-    pci_create_simple(d->bus, 0, "pbm");
+    pci_create_simple(d->bus, 0, "pbm-pci");

 
     /* APB secondary busses */
     pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
 
     /* APB secondary busses */
     pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,


@@ -386,6 +416,9 @@ static void pci_pbm_reset(DeviceState *d)
     for (i = 0; i < 8; i++) {
         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
     }
     for (i = 0; i < 8; i++) {
         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
     }

+    for (i = 0; i < 32; i++) {
+        s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
+    }

 
     if (s->nr_resets++ == 0) {
         /* Power on reset */
 
     if (s->nr_resets++ == 0) {
         /* Power on reset */


@@ -393,10 +426,15 @@ static void pci_pbm_reset(DeviceState *d)
     }
 }
 
     }
 }
 

+static const MemoryRegionOps pci_config_ops = {
+    .read = apb_pci_config_read,
+    .write = apb_pci_config_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+

 static int pci_pbm_init_device(SysBusDevice *dev)
 {
     APBState *s;
 static int pci_pbm_init_device(SysBusDevice *dev)
 {
     APBState *s;

-    int pci_config, apb_config, pci_ioport;

     unsigned int i;
 
     s = FROM_SYSBUS(APBState, dev);
     unsigned int i;
 
     s = FROM_SYSBUS(APBState, dev);


@@ -404,31 +442,26 @@ static int pci_pbm_init_device(SysBusDevice *dev)
         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
     }
     for (i = 0; i < 32; i++) {
         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
     }
     for (i = 0; i < 32; i++) {

-        sysbus_init_irq(dev, &s->pci_irqs[i]);
+        s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;

     }
     }

+    s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);

 
     /* apb_config */
 
     /* apb_config */

-    apb_config = cpu_register_io_memory(apb_config_read,
-                                        apb_config_write, s,
-                                        DEVICE_NATIVE_ENDIAN);
+    memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
+                          0x10000);

     /* at region 0 */
     /* at region 0 */

-    sysbus_init_mmio(dev, 0x10000ULL, apb_config);
+    sysbus_init_mmio(dev, &s->apb_config);

 
 

-    /* PCI configuration space */
-    s->pci_config_handler.read = apb_pci_config_read;
-    s->pci_config_handler.write = apb_pci_config_write;
-    pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
-                                               DEVICE_NATIVE_ENDIAN);
-    assert(pci_config >= 0);
+    memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
+                          0x1000000);

     /* at region 1 */
     /* at region 1 */

-    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
+    sysbus_init_mmio(dev, &s->pci_config);

 
     /* pci_ioport */
 
     /* pci_ioport */

-    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
-                                        pci_apb_iowrite, s,
-                                        DEVICE_NATIVE_ENDIAN);
+    memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
+                          "apb-pci-ioport", 0x10000);

     /* at region 2 */
     /* at region 2 */

-    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
+    sysbus_init_mmio(dev, &s->pci_ioport);

 
     return 0;
 }
 
     return 0;
 }


@@ -443,42 +476,67 @@ static int pbm_pci_host_init(PCIDevice *d)
     return 0;
 }
 
     return 0;
 }
 

-static PCIDeviceInfo pbm_pci_host_info = {
-    .qdev.name = "pbm",
-    .qdev.size = sizeof(PCIDevice),
-    .init      = pbm_pci_host_init,
-    .vendor_id = PCI_VENDOR_ID_SUN,
-    .device_id = PCI_DEVICE_ID_SUN_SABRE,
-    .class_id  = PCI_CLASS_BRIDGE_HOST,
-    .is_bridge = 1,
+static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->init = pbm_pci_host_init;
+    k->vendor_id = PCI_VENDOR_ID_SUN;
+    k->device_id = PCI_DEVICE_ID_SUN_SABRE;
+    k->class_id = PCI_CLASS_BRIDGE_HOST;
+}
+
+static const TypeInfo pbm_pci_host_info = {
+    .name          = "pbm-pci",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PCIDevice),
+    .class_init    = pbm_pci_host_class_init,

 };
 
 };
 

-static SysBusDeviceInfo pbm_host_info = {
-    .qdev.name = "pbm",
-    .qdev.size = sizeof(APBState),
-    .qdev.reset = pci_pbm_reset,
-    .init = pci_pbm_init_device,
+static void pbm_host_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+    k->init = pci_pbm_init_device;
+    dc->reset = pci_pbm_reset;
+}
+
+static const TypeInfo pbm_host_info = {
+    .name          = "pbm",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(APBState),
+    .class_init    = pbm_host_class_init,

 };
 
 };
 

-static PCIDeviceInfo pbm_pci_bridge_info = {
-    .qdev.name = "pbm-bridge",
-    .qdev.size = sizeof(PCIBridge),
-    .qdev.vmsd = &vmstate_pci_device,
-    .qdev.reset = pci_bridge_reset,
-    .init = apb_pci_bridge_initfn,
-    .exit = pci_bridge_exitfn,
-    .vendor_id = PCI_VENDOR_ID_SUN,
-    .device_id = PCI_DEVICE_ID_SUN_SIMBA,
-    .revision = 0x11,
-    .config_write = pci_bridge_write_config,
-    .is_bridge = 1,
+static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->init = apb_pci_bridge_initfn;
+    k->exit = pci_bridge_exitfn;
+    k->vendor_id = PCI_VENDOR_ID_SUN;
+    k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
+    k->revision = 0x11;
+    k->config_write = pci_bridge_write_config;
+    k->is_bridge = 1;
+    dc->reset = pci_bridge_reset;
+    dc->vmsd = &vmstate_pci_device;
+}
+
+static const TypeInfo pbm_pci_bridge_info = {
+    .name          = "pbm-bridge",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PCIBridge),
+    .class_init    = pbm_pci_bridge_class_init,

 };
 
 };
 

-static void pbm_register_devices(void)
+static void pbm_register_types(void)

 {
 {

-    sysbus_register_withprop(&pbm_host_info);
-    pci_qdev_register(&pbm_pci_host_info);
-    pci_qdev_register(&pbm_pci_bridge_info);
+    type_register_static(&pbm_host_info);
+    type_register_static(&pbm_pci_host_info);
+    type_register_static(&pbm_pci_bridge_info);

 }
 
 }
 

-device_init(pbm_register_devices)
+type_init(pbm_register_types)