*/
#include "sysbus.h"
-#include "scsi-disk.h"
#include "scsi.h"
-
-/* debug ESP card */
-//#define DEBUG_ESP
+#include "esp.h"
+#include "trace.h"
/*
* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
*/
-#ifdef DEBUG_ESP
-#define DPRINTF(fmt, ...) \
- do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while (0)
-#endif
-
#define ESP_ERROR(fmt, ...) \
do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
struct ESPState {
SysBusDevice busdev;
- uint32_t it_shift;
- qemu_irq irq;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
+ qemu_irq irq;
+ uint32_t it_shift;
int32_t ti_size;
uint32_t ti_rptr, ti_wptr;
- uint8_t ti_buf[TI_BUFSZ];
- uint32_t sense;
+ uint32_t status;
uint32_t dma;
- SCSIDevice *scsi_dev[ESP_MAX_DEVS];
+ uint8_t ti_buf[TI_BUFSZ];
+ SCSIBus bus;
SCSIDevice *current_dev;
+ SCSIRequest *current_req;
uint8_t cmdbuf[TI_BUFSZ];
uint32_t cmdlen;
uint32_t do_cmd;
/* The size of the current DMA transfer. Zero if no transfer is in
progress. */
uint32_t dma_counter;
- uint8_t *async_buf;
+ int dma_enabled;
+
uint32_t async_len;
+ uint8_t *async_buf;
- espdma_memory_read_write dma_memory_read;
- espdma_memory_read_write dma_memory_write;
+ ESPDMAMemoryReadWriteFunc dma_memory_read;
+ ESPDMAMemoryReadWriteFunc dma_memory_write;
void *dma_opaque;
+ void (*dma_cb)(ESPState *s);
};
#define ESP_TCLO 0x0
#define CMD_TI 0x10
#define CMD_ICCS 0x11
#define CMD_MSGACC 0x12
+#define CMD_PAD 0x18
#define CMD_SATN 0x1a
+#define CMD_SEL 0x41
#define CMD_SELATN 0x42
#define CMD_SELATNS 0x43
#define CMD_ENSEL 0x44
if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
s->rregs[ESP_RSTAT] |= STAT_INT;
qemu_irq_raise(s->irq);
+ trace_esp_raise_irq();
}
}
if (s->rregs[ESP_RSTAT] & STAT_INT) {
s->rregs[ESP_RSTAT] &= ~STAT_INT;
qemu_irq_lower(s->irq);
+ trace_esp_lower_irq();
+ }
+}
+
+static void esp_dma_enable(void *opaque, int irq, int level)
+{
+ DeviceState *d = opaque;
+ ESPState *s = container_of(d, ESPState, busdev.qdev);
+
+ if (level) {
+ s->dma_enabled = 1;
+ trace_esp_dma_enable();
+ if (s->dma_cb) {
+ s->dma_cb(s);
+ s->dma_cb = NULL;
+ }
+ } else {
+ trace_esp_dma_disable();
+ s->dma_enabled = 0;
+ }
+}
+
+static void esp_request_cancelled(SCSIRequest *req)
+{
+ ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
+
+ if (req == s->current_req) {
+ scsi_req_unref(s->current_req);
+ s->current_req = NULL;
+ s->current_dev = NULL;
}
}
} else {
dmalen = s->ti_size;
memcpy(buf, s->ti_buf, dmalen);
- buf[0] = 0;
+ buf[0] = buf[2] >> 5;
}
- DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
+ trace_esp_get_cmd(dmalen, target);
s->ti_size = 0;
s->ti_rptr = 0;
s->ti_wptr = 0;
- if (s->current_dev) {
+ if (s->current_req) {
/* Started a new command before the old one finished. Cancel it. */
- s->current_dev->cancel_io(s->current_dev, 0);
+ scsi_req_cancel(s->current_req);
s->async_len = 0;
}
- if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
+ s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
+ if (!s->current_dev) {
// No such drive
s->rregs[ESP_RSTAT] = 0;
s->rregs[ESP_RINTR] = INTR_DC;
esp_raise_irq(s);
return 0;
}
- s->current_dev = s->scsi_dev[target];
return dmalen;
}
-static void do_cmd(ESPState *s, uint8_t *buf)
+static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
{
int32_t datalen;
int lun;
+ SCSIDevice *current_lun;
- DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
- lun = buf[0] & 7;
- datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun);
+ trace_esp_do_busid_cmd(busid);
+ lun = busid & 7;
+ current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
+ s->current_req = scsi_req_new(current_lun, 0, lun, buf, NULL);
+ datalen = scsi_req_enqueue(s->current_req);
s->ti_size = datalen;
if (datalen != 0) {
s->rregs[ESP_RSTAT] = STAT_TC;
s->dma_counter = 0;
if (datalen > 0) {
s->rregs[ESP_RSTAT] |= STAT_DI;
- s->current_dev->read_data(s->current_dev, 0);
} else {
s->rregs[ESP_RSTAT] |= STAT_DO;
- s->current_dev->write_data(s->current_dev, 0);
}
+ scsi_req_continue(s->current_req);
}
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
}
+static void do_cmd(ESPState *s, uint8_t *buf)
+{
+ uint8_t busid = buf[0];
+
+ do_busid_cmd(s, &buf[1], busid);
+}
+
static void handle_satn(ESPState *s)
{
uint8_t buf[32];
int len;
+ if (!s->dma_enabled) {
+ s->dma_cb = handle_satn;
+ return;
+ }
len = get_cmd(s, buf);
if (len)
do_cmd(s, buf);
}
+static void handle_s_without_atn(ESPState *s)
+{
+ uint8_t buf[32];
+ int len;
+
+ if (!s->dma_enabled) {
+ s->dma_cb = handle_s_without_atn;
+ return;
+ }
+ len = get_cmd(s, buf);
+ if (len) {
+ do_busid_cmd(s, buf, 0);
+ }
+}
+
static void handle_satn_stop(ESPState *s)
{
+ if (!s->dma_enabled) {
+ s->dma_cb = handle_satn_stop;
+ return;
+ }
s->cmdlen = get_cmd(s, s->cmdbuf);
if (s->cmdlen) {
- DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
+ trace_esp_handle_satn_stop(s->cmdlen);
s->do_cmd = 1;
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
static void write_response(ESPState *s)
{
- DPRINTF("Transfer status (sense=%d)\n", s->sense);
- s->ti_buf[0] = s->sense;
+ trace_esp_write_response(s->status);
+ s->ti_buf[0] = s->status;
s->ti_buf[1] = 0;
if (s->dma) {
s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
to_device = (s->ti_size < 0);
len = s->dma_left;
if (s->do_cmd) {
- DPRINTF("command len %d + %d\n", s->cmdlen, len);
+ trace_esp_do_dma(s->cmdlen, len);
s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
s->ti_size = 0;
s->cmdlen = 0;
else
s->ti_size -= len;
if (s->async_len == 0) {
- if (to_device) {
- // ti_size is negative
- s->current_dev->write_data(s->current_dev, 0);
- } else {
- s->current_dev->read_data(s->current_dev, 0);
- /* If there is still data to be read from the device then
- complete the DMA operation immediately. Otherwise defer
- until the scsi layer has completed. */
- if (s->dma_left == 0 && s->ti_size > 0) {
- esp_dma_done(s);
- }
+ scsi_req_continue(s->current_req);
+ /* If there is still data to be read from the device then
+ complete the DMA operation immediately. Otherwise defer
+ until the scsi layer has completed. */
+ if (to_device || s->dma_left != 0 || s->ti_size == 0) {
+ return;
}
- } else {
- /* Partially filled a scsi buffer. Complete immediately. */
- esp_dma_done(s);
}
+
+ /* Partially filled a scsi buffer. Complete immediately. */
+ esp_dma_done(s);
}
-static void esp_command_complete(void *opaque, int reason, uint32_t tag,
- uint32_t arg)
+static void esp_command_complete(SCSIRequest *req, uint32_t status)
{
- ESPState *s = (ESPState *)opaque;
+ ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
- if (reason == SCSI_REASON_DONE) {
- DPRINTF("SCSI Command complete\n");
- if (s->ti_size != 0)
- DPRINTF("SCSI command completed unexpectedly\n");
- s->ti_size = 0;
- s->dma_left = 0;
- s->async_len = 0;
- if (arg)
- DPRINTF("Command failed\n");
- s->sense = arg;
- s->rregs[ESP_RSTAT] = STAT_ST;
- esp_dma_done(s);
+ trace_esp_command_complete();
+ if (s->ti_size != 0) {
+ trace_esp_command_complete_unexpected();
+ }
+ s->ti_size = 0;
+ s->dma_left = 0;
+ s->async_len = 0;
+ if (status) {
+ trace_esp_command_complete_fail();
+ }
+ s->status = status;
+ s->rregs[ESP_RSTAT] = STAT_ST;
+ esp_dma_done(s);
+ if (s->current_req) {
+ scsi_req_unref(s->current_req);
+ s->current_req = NULL;
s->current_dev = NULL;
- } else {
- DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
- s->async_len = arg;
- s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
- if (s->dma_left) {
- esp_do_dma(s);
- } else if (s->dma_counter != 0 && s->ti_size <= 0) {
- /* If this was the last part of a DMA transfer then the
- completion interrupt is deferred to here. */
- esp_dma_done(s);
- }
+ }
+}
+
+static void esp_transfer_data(SCSIRequest *req, uint32_t len)
+{
+ ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
+
+ trace_esp_transfer_data(s->dma_left, s->ti_size);
+ s->async_len = len;
+ s->async_buf = scsi_req_get_buf(req);
+ if (s->dma_left) {
+ esp_do_dma(s);
+ } else if (s->dma_counter != 0 && s->ti_size <= 0) {
+ /* If this was the last part of a DMA transfer then the
+ completion interrupt is deferred to here. */
+ esp_dma_done(s);
}
}
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
else
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
- DPRINTF("Transfer Information len %d\n", minlen);
+ trace_esp_handle_ti(minlen);
if (s->dma) {
s->dma_left = minlen;
s->rregs[ESP_RSTAT] &= ~STAT_TC;
esp_do_dma(s);
} else if (s->do_cmd) {
- DPRINTF("command len %d\n", s->cmdlen);
+ trace_esp_handle_ti_cmd(s->cmdlen);
s->ti_size = 0;
s->cmdlen = 0;
s->do_cmd = 0;
}
}
-static void esp_reset(void *opaque)
+static void esp_hard_reset(DeviceState *d)
{
- ESPState *s = opaque;
+ ESPState *s = container_of(d, ESPState, busdev.qdev);
memset(s->rregs, 0, ESP_REGS);
memset(s->wregs, 0, ESP_REGS);
s->ti_wptr = 0;
s->dma = 0;
s->do_cmd = 0;
+ s->dma_cb = NULL;
s->rregs[ESP_CFG1] = 7;
}
+static void esp_soft_reset(DeviceState *d)
+{
+ ESPState *s = container_of(d, ESPState, busdev.qdev);
+
+ qemu_irq_lower(s->irq);
+ esp_hard_reset(d);
+}
+
static void parent_esp_reset(void *opaque, int irq, int level)
{
- if (level)
- esp_reset(opaque);
+ if (level) {
+ esp_soft_reset(opaque);
+ }
+}
+
+static void esp_gpio_demux(void *opaque, int irq, int level)
+{
+ switch (irq) {
+ case 0:
+ parent_esp_reset(opaque, irq, level);
+ break;
+ case 1:
+ esp_dma_enable(opaque, irq, level);
+ break;
+ }
}
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
- uint32_t saddr;
+ uint32_t saddr, old_val;
saddr = addr >> s->it_shift;
- DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
+ trace_esp_mem_readb(saddr, s->rregs[saddr]);
switch (saddr) {
case ESP_FIFO:
if (s->ti_size > 0) {
}
break;
case ESP_RINTR:
- // Clear interrupt/error status bits
- s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE);
+ /* Clear sequence step, interrupt register and all status bits
+ except TC */
+ old_val = s->rregs[ESP_RINTR];
+ s->rregs[ESP_RINTR] = 0;
+ s->rregs[ESP_RSTAT] &= ~STAT_TC;
+ s->rregs[ESP_RSEQ] = SEQ_CD;
esp_lower_irq(s);
- break;
+
+ return old_val;
default:
break;
}
uint32_t saddr;
saddr = addr >> s->it_shift;
- DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
- val);
+ trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
switch (saddr) {
case ESP_TCLO:
case ESP_TCMID:
}
switch(val & CMD_CMD) {
case CMD_NOP:
- DPRINTF("NOP (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_nop(val);
break;
case CMD_FLUSH:
- DPRINTF("Flush FIFO (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_flush(val);
//s->ti_size = 0;
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
break;
case CMD_RESET:
- DPRINTF("Chip reset (%2.2x)\n", val);
- esp_reset(s);
+ trace_esp_mem_writeb_cmd_reset(val);
+ esp_soft_reset(&s->busdev.qdev);
break;
case CMD_BUSRESET:
- DPRINTF("Bus reset (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_bus_reset(val);
s->rregs[ESP_RINTR] = INTR_RST;
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
esp_raise_irq(s);
handle_ti(s);
break;
case CMD_ICCS:
- DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_iccs(val);
write_response(s);
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSTAT] |= STAT_MI;
break;
case CMD_MSGACC:
- DPRINTF("Message Accepted (%2.2x)\n", val);
- write_response(s);
+ trace_esp_mem_writeb_cmd_msgacc(val);
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = 0;
+ s->rregs[ESP_RFLAGS] = 0;
+ esp_raise_irq(s);
+ break;
+ case CMD_PAD:
+ trace_esp_mem_writeb_cmd_pad(val);
+ s->rregs[ESP_RSTAT] = STAT_TC;
+ s->rregs[ESP_RINTR] = INTR_FC;
+ s->rregs[ESP_RSEQ] = 0;
break;
case CMD_SATN:
- DPRINTF("Set ATN (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_satn(val);
+ break;
+ case CMD_SEL:
+ trace_esp_mem_writeb_cmd_sel(val);
+ handle_s_without_atn(s);
break;
case CMD_SELATN:
- DPRINTF("Set ATN (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_selatn(val);
handle_satn(s);
break;
case CMD_SELATNS:
- DPRINTF("Set ATN & stop (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_selatns(val);
handle_satn_stop(s);
break;
case CMD_ENSEL:
- DPRINTF("Enable selection (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_ensel(val);
s->rregs[ESP_RINTR] = 0;
break;
default:
s->wregs[saddr] = val;
}
-static CPUReadMemoryFunc *esp_mem_read[3] = {
+static CPUReadMemoryFunc * const esp_mem_read[3] = {
esp_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *esp_mem_write[3] = {
+static CPUWriteMemoryFunc * const esp_mem_write[3] = {
esp_mem_writeb,
NULL,
esp_mem_writeb,
};
-static void esp_save(QEMUFile *f, void *opaque)
-{
- ESPState *s = opaque;
-
- qemu_put_buffer(f, s->rregs, ESP_REGS);
- qemu_put_buffer(f, s->wregs, ESP_REGS);
- qemu_put_sbe32s(f, &s->ti_size);
- qemu_put_be32s(f, &s->ti_rptr);
- qemu_put_be32s(f, &s->ti_wptr);
- qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
- qemu_put_be32s(f, &s->sense);
- qemu_put_be32s(f, &s->dma);
- qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ);
- qemu_put_be32s(f, &s->cmdlen);
- qemu_put_be32s(f, &s->do_cmd);
- qemu_put_be32s(f, &s->dma_left);
- // There should be no transfers in progress, so dma_counter is not saved
-}
-
-static int esp_load(QEMUFile *f, void *opaque, int version_id)
-{
- ESPState *s = opaque;
-
- if (version_id != 3)
- return -EINVAL; // Cannot emulate 2
-
- qemu_get_buffer(f, s->rregs, ESP_REGS);
- qemu_get_buffer(f, s->wregs, ESP_REGS);
- qemu_get_sbe32s(f, &s->ti_size);
- qemu_get_be32s(f, &s->ti_rptr);
- qemu_get_be32s(f, &s->ti_wptr);
- qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
- qemu_get_be32s(f, &s->sense);
- qemu_get_be32s(f, &s->dma);
- qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ);
- qemu_get_be32s(f, &s->cmdlen);
- qemu_get_be32s(f, &s->do_cmd);
- qemu_get_be32s(f, &s->dma_left);
-
- return 0;
-}
-
-static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id)
-{
- ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host));
-
- if (id < 0) {
- for (id = 0; id < ESP_MAX_DEVS; id++) {
- if (id == (s->rregs[ESP_CFG1] & 0x7))
- continue;
- if (s->scsi_dev[id] == NULL)
- break;
- }
- }
- if (id >= ESP_MAX_DEVS) {
- DPRINTF("Bad Device ID %d\n", id);
- return;
- }
- if (s->scsi_dev[id]) {
- DPRINTF("Destroying device %d\n", id);
- s->scsi_dev[id]->destroy(s->scsi_dev[id]);
+static const VMStateDescription vmstate_esp = {
+ .name ="esp",
+ .version_id = 3,
+ .minimum_version_id = 3,
+ .minimum_version_id_old = 3,
+ .fields = (VMStateField []) {
+ VMSTATE_BUFFER(rregs, ESPState),
+ VMSTATE_BUFFER(wregs, ESPState),
+ VMSTATE_INT32(ti_size, ESPState),
+ VMSTATE_UINT32(ti_rptr, ESPState),
+ VMSTATE_UINT32(ti_wptr, ESPState),
+ VMSTATE_BUFFER(ti_buf, ESPState),
+ VMSTATE_UINT32(status, ESPState),
+ VMSTATE_UINT32(dma, ESPState),
+ VMSTATE_BUFFER(cmdbuf, ESPState),
+ VMSTATE_UINT32(cmdlen, ESPState),
+ VMSTATE_UINT32(do_cmd, ESPState),
+ VMSTATE_UINT32(dma_left, ESPState),
+ VMSTATE_END_OF_LIST()
}
- DPRINTF("Attaching block device %d\n", id);
- /* Command queueing is not implemented. */
- s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
- if (s->scsi_dev[id] == NULL)
- s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
-}
+};
void esp_init(target_phys_addr_t espaddr, int it_shift,
- espdma_memory_read_write dma_memory_read,
- espdma_memory_read_write dma_memory_write,
- void *dma_opaque, qemu_irq irq, qemu_irq *reset)
+ ESPDMAMemoryReadWriteFunc dma_memory_read,
+ ESPDMAMemoryReadWriteFunc dma_memory_write,
+ void *dma_opaque, qemu_irq irq, qemu_irq *reset,
+ qemu_irq *dma_enable)
{
DeviceState *dev;
SysBusDevice *s;
esp->dma_memory_write = dma_memory_write;
esp->dma_opaque = dma_opaque;
esp->it_shift = it_shift;
- qdev_init(dev);
+ /* XXX for now until rc4030 has been changed to use DMA enable signal */
+ esp->dma_enabled = 1;
+ qdev_init_nofail(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, espaddr);
+ *reset = qdev_get_gpio_in(dev, 0);
+ *dma_enable = qdev_get_gpio_in(dev, 1);
}
-static void esp_init1(SysBusDevice *dev)
+static const struct SCSIBusInfo esp_scsi_info = {
+ .tcq = false,
+ .max_target = ESP_MAX_DEVS,
+ .max_lun = 7,
+
+ .transfer_data = esp_transfer_data,
+ .complete = esp_command_complete,
+ .cancel = esp_request_cancelled
+};
+
+static int esp_init1(SysBusDevice *dev)
{
ESPState *s = FROM_SYSBUS(ESPState, dev);
int esp_io_memory;
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
- esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
+ esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
- esp_reset(s);
-
- register_savevm("esp", -1, 3, esp_save, esp_load, s);
- qemu_register_reset(esp_reset, s);
-
- qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
+ qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
- scsi_bus_new(&dev->qdev, esp_scsi_attach);
+ scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
+ return scsi_bus_legacy_handle_cmdline(&s->bus);
}
+static SysBusDeviceInfo esp_info = {
+ .init = esp_init1,
+ .qdev.name = "esp",
+ .qdev.size = sizeof(ESPState),
+ .qdev.vmsd = &vmstate_esp,
+ .qdev.reset = esp_hard_reset,
+ .qdev.props = (Property[]) {
+ {.name = NULL}
+ }
+};
+
static void esp_register_devices(void)
{
- sysbus_register_dev("esp", sizeof(ESPState), esp_init1);
+ sysbus_register_withprop(&esp_info);
}
device_init(esp_register_devices)
projects / qemu.git / blobdiff