#include "cpu.h"
#include "hw/hw.h"
#include "hw/timer/m48t59.h"
-#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "exec/address-spaces.h"
#include "trace.h"
#include "elf.h"
-#include "qemu/cutils.h"
+#include "qemu/units.h"
#include "kvm_ppc.h"
/* SMP is not enabled, for now */
#define CFG_ADDR 0xf0000510
-#define BIOS_SIZE (1024 * 1024)
+#define BIOS_SIZE (1 * MiB)
#define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
/* ISA IO ports bridge */
#define PPC_IO_BASE 0x80000000
-/* PowerPC control and status registers */
-#if 0 // Not used
-static struct {
- /* IDs */
- uint32_t veni_devi;
- uint32_t revi;
- /* Control and status */
- uint32_t gcsr;
- uint32_t xcfr;
- uint32_t ct32;
- uint32_t mcsr;
- /* General purpose registers */
- uint32_t gprg[6];
- /* Exceptions */
- uint32_t feen;
- uint32_t fest;
- uint32_t fema;
- uint32_t fecl;
- uint32_t eeen;
- uint32_t eest;
- uint32_t eecl;
- uint32_t eeint;
- uint32_t eemck0;
- uint32_t eemck1;
- /* Error diagnostic */
-} XCSR;
-
-static void PPC_XCSR_writeb (void *opaque,
- hwaddr addr, uint32_t value)
-{
- printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
- value);
-}
-
-static void PPC_XCSR_writew (void *opaque,
- hwaddr addr, uint32_t value)
-{
- printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
- value);
-}
-
-static void PPC_XCSR_writel (void *opaque,
- hwaddr addr, uint32_t value)
-{
- printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
- value);
-}
-
-static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
-{
- uint32_t retval = 0;
-
- printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
- retval);
-
- return retval;
-}
-
-static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
-{
- uint32_t retval = 0;
-
- printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
- retval);
-
- return retval;
-}
-
-static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
-{
- uint32_t retval = 0;
-
- printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
- retval);
-
- return retval;
-}
-
-static const MemoryRegionOps PPC_XCSR_ops = {
- .old_mmio = {
- .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
- .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
- },
- .endianness = DEVICE_LITTLE_ENDIAN,
-};
-
-#endif
-
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
typedef struct sysctrl_t {
qemu_irq reset_irq;
}
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
+ qdev_prop_set_bit(dev, "is-legacy-prep", true);
pcihost = PCI_HOST_BRIDGE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
qdev_init_nofail(dev);
nb_nics1 = NE2000_NB_MAX;
for(i = 0; i < nb_nics1; i++) {
if (nd_table[i].model == NULL) {
- nd_table[i].model = g_strdup("ne2k_isa");
+ nd_table[i].model = g_strdup("ne2k_isa");
}
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
for(i = 0; i < MAX_IDE_BUS; i++) {
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[2 * i],
- hd[2 * i + 1]);
+ hd[2 * i + 1]);
}
cpu = POWERPC_CPU(first_cpu);
portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
- /* PowerPC control and status register group */
-#if 0
- memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
- memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
-#endif
+ /*
+ * PowerPC control and status register group: unimplemented,
+ * would be at address 0xFEFF0000.
+ */
if (machine_usb(machine)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
static void prep_machine_init(MachineClass *mc)
{
+ mc->deprecation_reason = "use 40p machine type instead";
mc->desc = "PowerPC PREP platform";
mc->init = ppc_prep_init;
mc->block_default_type = IF_IDE;
mc->max_cpus = MAX_CPUS;
mc->default_boot_order = "cad";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
+ mc->default_display = "std";
}
static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
rtc_set_memory(rtc, 0x3e, checksum & 0xff);
rtc_set_memory(rtc, 0x2f, checksum >> 8);
rtc_set_memory(rtc, 0x3f, checksum >> 8);
+
+ object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
+ "date", NULL);
}
return 0;
}
CPUPPCState *env = NULL;
uint16_t cmos_checksum;
PowerPCCPU *cpu;
- DeviceState *dev;
- SysBusDevice *pcihost;
+ DeviceState *dev, *i82378_dev;
+ SysBusDevice *pcihost, *s;
Nvram *m48t59 = NULL;
PCIBus *pci_bus;
ISABus *isa_bus;
/* PCI host */
dev = qdev_create(NULL, "raven-pcihost");
if (!bios_name) {
- bios_name = BIOS_FILENAME;
+ bios_name = "openbios-ppc";
}
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
}
/* PCI -> ISA bridge */
- dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
- qdev_connect_gpio_out(dev, 0,
+ i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
+ qdev_connect_gpio_out(i82378_dev, 0,
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
- sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
- sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
- sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
- sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
- isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
+ isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
/* Memory controller */
dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
/* add some more devices */
if (defaults_enabled()) {
- isa_create_simple(isa_bus, TYPE_I8042);
m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
dev = DEVICE(isa_create(isa_bus, "cs4231a"));
qdev_prop_set_uint32(dev, "equipment", 0xc0);
qdev_init_nofail(dev);
- lsi53c810_create(pci_bus, PCI_DEVFN(1, 0));
+ dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
+ "lsi53c810"));
+ lsi53c8xx_handle_legacy_cmdline(dev);
+ qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
/* XXX: s3-trio at PCI_DEVFN(2, 0) */
pci_vga_init(pci_bus);
}
/* Prepare firmware configuration for OpenBIOS */
- fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
+ dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ fw_cfg = FW_CFG(dev);
+ qdev_prop_set_uint32(dev, "data_width", 1);
+ qdev_prop_set_bit(dev, "dma_enabled", false);
+ object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
+ OBJECT(fw_cfg), NULL);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(s, 0, CFG_ADDR);
+ sysbus_mmio_map(s, 1, CFG_ADDR + 2);
if (machine->kernel_filename) {
/* load kernel */
mc->desc = "IBM RS/6000 7020 (40p)",
mc->init = ibm_40p_init;
mc->max_cpus = 1;
- mc->pci_allow_0_address = true;
- mc->default_ram_size = 128 * M_BYTE;
+ mc->default_ram_size = 128 * MiB;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
+ mc->default_display = "std";
}
DEFINE_MACHINE("40p", ibm_40p_machine_init)
projects / qemu.git / blobdiff