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block: drive_init(): Improve CHS setting error message
[qemu.git] / hw / etraxfs_dma.c
diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
index d2604fb9fa15d524653acd1be0e6fd205dfcbd4d..c205ec1b8f443f297f7232c0b8e34d9698c7c7a7 100644 (file)
--- a/hw/etraxfs_dma.c
+++ b/hw/etraxfs_dma.c
@@ -31,27 +31,27 @@
 
 #define D(x)
 
 
 #define D(x)
 
-#define RW_DATA           0x0
-#define RW_SAVED_DATA     0x58
-#define RW_SAVED_DATA_BUF 0x5c
-#define RW_GROUP          0x60
-#define RW_GROUP_DOWN     0x7c
-#define RW_CMD            0x80
-#define RW_CFG            0x84
-#define RW_STAT           0x88
-#define RW_INTR_MASK      0x8c
-#define RW_ACK_INTR       0x90
-#define R_INTR            0x94
-#define R_MASKED_INTR     0x98
-#define RW_STREAM_CMD     0x9c
-
-#define DMA_REG_MAX   0x100
+#define RW_DATA           (0x0 / 4)
+#define RW_SAVED_DATA     (0x58 / 4)
+#define RW_SAVED_DATA_BUF (0x5c / 4)
+#define RW_GROUP          (0x60 / 4)
+#define RW_GROUP_DOWN     (0x7c / 4)
+#define RW_CMD            (0x80 / 4)
+#define RW_CFG            (0x84 / 4)
+#define RW_STAT           (0x88 / 4)
+#define RW_INTR_MASK      (0x8c / 4)
+#define RW_ACK_INTR       (0x90 / 4)
+#define R_INTR            (0x94 / 4)
+#define R_MASKED_INTR     (0x98 / 4)
+#define RW_STREAM_CMD     (0x9c / 4)
+
+#define DMA_REG_MAX       (0x100 / 4)
 
 /* descriptors */
 
 // ------------------------------------------------------------ dma_descr_group
 typedef struct dma_descr_group {
 
 /* descriptors */
 
 // ------------------------------------------------------------ dma_descr_group
 typedef struct dma_descr_group {
-  struct dma_descr_group       *next;
+  uint32_t                      next;
   unsigned                      eol        : 1;
   unsigned                      tol        : 1;
   unsigned                      bol        : 1;
   unsigned                      eol        : 1;
   unsigned                      tol        : 1;
   unsigned                      bol        : 1;
@@ -71,7 +71,7 @@ typedef struct dma_descr_group {
 
 // ---------------------------------------------------------- dma_descr_context
 typedef struct dma_descr_context {
 
 // ---------------------------------------------------------- dma_descr_context
 typedef struct dma_descr_context {
-  struct dma_descr_context     *next;
+  uint32_t                      next;
   unsigned                      eol        : 1;
   unsigned                                 : 3;
   unsigned                      intr       : 1;
   unsigned                      eol        : 1;
   unsigned                                 : 3;
   unsigned                      intr       : 1;
@@ -85,14 +85,14 @@ typedef struct dma_descr_context {
   unsigned                      md2;
   unsigned                      md3;
   unsigned                      md4;
   unsigned                      md2;
   unsigned                      md3;
   unsigned                      md4;
-  struct dma_descr_data        *saved_data;
-  char                         *saved_data_buf;
+  uint32_t                      saved_data;
+  uint32_t                      saved_data_buf;
 } dma_descr_context;
 
 // ------------------------------------------------------------- dma_descr_data
 typedef struct dma_descr_data {
 } dma_descr_context;
 
 // ------------------------------------------------------------- dma_descr_data
 typedef struct dma_descr_data {
-  struct dma_descr_data        *next;
-  char                         *buf;
+  uint32_t                      next;
+  uint32_t                      buf;
   unsigned                      eol        : 1;
   unsigned                                 : 2;
   unsigned                      out_eop    : 1;
   unsigned                      eol        : 1;
   unsigned                                 : 2;
   unsigned                      out_eop    : 1;
@@ -103,7 +103,7 @@ typedef struct dma_descr_data {
   unsigned                      in_eop     : 1;
   unsigned                                 : 4;
   unsigned                      md         : 16;
   unsigned                      in_eop     : 1;
   unsigned                                 : 4;
   unsigned                      md         : 16;
-  char                         *after;
+  uint32_t                      after;
 } dma_descr_data;
 
 /* Constants */
 } dma_descr_data;
 
 /* Constants */
@@ -165,11 +165,9 @@ enum dma_ch_state
 
 struct fs_dma_channel
 {
 
 struct fs_dma_channel
 {
-       int regmap;
-       qemu_irq *irq;
+       qemu_irq irq;
        struct etraxfs_dma_client *client;
 
        struct etraxfs_dma_client *client;
 
-
        /* Internal status.  */
        int stream_cmd_src;
        enum dma_ch_state state;
        /* Internal status.  */
        int stream_cmd_src;
        enum dma_ch_state state;
@@ -187,15 +185,16 @@ struct fs_dma_channel
 
 struct fs_dma_ctrl
 {
 
 struct fs_dma_ctrl
 {
-       CPUState *env;
-       target_phys_addr_t base;
-
+       int map;
        int nr_channels;
        struct fs_dma_channel *channels;
 
         QEMUBH *bh;
 };
 
        int nr_channels;
        struct fs_dma_channel *channels;
 
         QEMUBH *bh;
 };
 
+static void DMA_run(void *opaque);
+static int channel_out_run(struct fs_dma_ctrl *ctrl, int c);
+
 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
 {
        return ctrl->channels[c].regs[reg];
 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
 {
        return ctrl->channels[c].regs[reg];
@@ -212,10 +211,10 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
                && ctrl->channels[c].client;
 }
 
                && ctrl->channels[c].client;
 }
 
-static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
+static inline int fs_channel(target_phys_addr_t addr)
 {
        /* Every channel has a 0x2000 ctrl register map.  */
 {
        /* Every channel has a 0x2000 ctrl register map.  */
-       return (addr - base) >> 13;
+       return addr >> 13;
 }
 
 #ifdef USE_THIS_DEAD_CODE
 }
 
 #ifdef USE_THIS_DEAD_CODE
@@ -232,18 +231,18 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
 static void dump_c(int ch, struct dma_descr_context *c)
 {
        printf("%s ch=%d\n", __func__, ch);
 static void dump_c(int ch, struct dma_descr_context *c)
 {
        printf("%s ch=%d\n", __func__, ch);
-       printf("next=%p\n", c->next);
-       printf("saved_data=%p\n", c->saved_data);
-       printf("saved_data_buf=%p\n", c->saved_data_buf);
+       printf("next=%x\n", c->next);
+       printf("saved_data=%x\n", c->saved_data);
+       printf("saved_data_buf=%x\n", c->saved_data_buf);
        printf("eol=%x\n", (uint32_t) c->eol);
 }
 
 static void dump_d(int ch, struct dma_descr_data *d)
 {
        printf("%s ch=%d\n", __func__, ch);
        printf("eol=%x\n", (uint32_t) c->eol);
 }
 
 static void dump_d(int ch, struct dma_descr_data *d)
 {
        printf("%s ch=%d\n", __func__, ch);
-       printf("next=%p\n", d->next);
-       printf("buf=%p\n", d->buf);
-       printf("after=%p\n", d->after);
+       printf("next=%x\n", d->next);
+       printf("buf=%x\n", d->buf);
+       printf("after=%x\n", d->after);
        printf("intr=%x\n", (uint32_t) d->intr);
        printf("out_eop=%x\n", (uint32_t) d->out_eop);
        printf("in_eop=%x\n", (uint32_t) d->in_eop);
        printf("intr=%x\n", (uint32_t) d->intr);
        printf("out_eop=%x\n", (uint32_t) d->out_eop);
        printf("in_eop=%x\n", (uint32_t) d->in_eop);
@@ -273,7 +272,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 
        /* Load and decode. FIXME: handle endianness.  */
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 
        /* Load and decode. FIXME: handle endianness.  */
-       D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
+       D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
        cpu_physical_memory_read (addr,
                                  (void *) &ctrl->channels[c].current_d, 
                                  sizeof ctrl->channels[c].current_d);
        cpu_physical_memory_read (addr,
                                  (void *) &ctrl->channels[c].current_d, 
                                  sizeof ctrl->channels[c].current_d);
@@ -287,7 +286,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
 
        /* Encode and store. FIXME: handle endianness.  */
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
 
        /* Encode and store. FIXME: handle endianness.  */
-       D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
+       D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
        D(dump_d(c, &ctrl->channels[c].current_d));
        cpu_physical_memory_write (addr,
                                  (void *) &ctrl->channels[c].current_c,
        D(dump_d(c, &ctrl->channels[c].current_d));
        cpu_physical_memory_write (addr,
                                  (void *) &ctrl->channels[c].current_c,
@@ -299,7 +298,7 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 
        /* Encode and store. FIXME: handle endianness.  */
        target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 
        /* Encode and store. FIXME: handle endianness.  */
-       D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
+       D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
        cpu_physical_memory_write (addr,
                                  (void *) &ctrl->channels[c].current_d, 
                                  sizeof ctrl->channels[c].current_d);
        cpu_physical_memory_write (addr,
                                  (void *) &ctrl->channels[c].current_d, 
                                  sizeof ctrl->channels[c].current_d);
@@ -316,8 +315,12 @@ static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
        {
                ctrl->channels[c].eol = 0;
                ctrl->channels[c].state = RUNNING;
        {
                ctrl->channels[c].eol = 0;
                ctrl->channels[c].state = RUNNING;
+               if (!ctrl->channels[c].input)
+                       channel_out_run(ctrl, c);
        } else
                printf("WARNING: starting DMA ch %d with no client\n", c);
        } else
                printf("WARNING: starting DMA ch %d with no client\n", c);
+
+        qemu_bh_schedule_idle(ctrl->bh);
 }
 
 static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
 }
 
 static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
@@ -342,11 +345,14 @@ static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
        /* If the current descriptor cleared the eol flag and we had already
           reached eol state, do the continue.  */
        if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
        /* If the current descriptor cleared the eol flag and we had already
           reached eol state, do the continue.  */
        if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
-               D(printf("continue %d ok %p\n", c,
+               D(printf("continue %d ok %x\n", c,
                         ctrl->channels[c].current_d.next));
                ctrl->channels[c].regs[RW_SAVED_DATA] =
                        (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
                channel_load_d(ctrl, c);
                         ctrl->channels[c].current_d.next));
                ctrl->channels[c].regs[RW_SAVED_DATA] =
                        (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
                channel_load_d(ctrl, c);
+               ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
+                       (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
+
                channel_start(ctrl, c);
        }
        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
                channel_start(ctrl, c);
        }
        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
@@ -367,7 +373,6 @@ static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
 
        if (cmd & regk_dma_load_c) {
                channel_load_c(ctrl, c);
 
        if (cmd & regk_dma_load_c) {
                channel_load_c(ctrl, c);
-               channel_start(ctrl, c);
        }
 }
 
        }
 }
 
@@ -385,27 +390,27 @@ static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
                 c,
                 ctrl->channels[c].regs[R_MASKED_INTR]));
 
                 c,
                 ctrl->channels[c].regs[R_MASKED_INTR]));
 
-        if (ctrl->channels[c].regs[R_MASKED_INTR])
-                qemu_irq_raise(ctrl->channels[c].irq[0]);
-        else
-                qemu_irq_lower(ctrl->channels[c].irq[0]);
+        qemu_set_irq(ctrl->channels[c].irq,
+                    !!ctrl->channels[c].regs[R_MASKED_INTR]);
 }
 
 }
 
-static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
+static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
 {
        uint32_t len;
        uint32_t saved_data_buf;
        unsigned char buf[2 * 1024];
 
 {
        uint32_t len;
        uint32_t saved_data_buf;
        unsigned char buf[2 * 1024];
 
-       while (ctrl->channels[c].eol != 1) {
-               saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
+       if (ctrl->channels[c].eol)
+               return 0;
 
 
-               D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
+       do {
+               D(printf("ch=%d buf=%x after=%x\n",
                         c,
                         (uint32_t)ctrl->channels[c].current_d.buf,
                         c,
                         (uint32_t)ctrl->channels[c].current_d.buf,
-                        (uint32_t)ctrl->channels[c].current_d.after,
-                        saved_data_buf));
+                        (uint32_t)ctrl->channels[c].current_d.after));
 
 
+               channel_load_d(ctrl, c);
+               saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
                len = (uint32_t)(unsigned long)
                        ctrl->channels[c].current_d.after;
                len -= saved_data_buf;
                len = (uint32_t)(unsigned long)
                        ctrl->channels[c].current_d.after;
                len -= saved_data_buf;
@@ -437,10 +442,12 @@ static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
                        if (ctrl->channels[c].current_d.intr) {
                                /* TODO: signal eop to the client.  */
                                /* data intr.  */
                        if (ctrl->channels[c].current_d.intr) {
                                /* TODO: signal eop to the client.  */
                                /* data intr.  */
-                               D(printf("signal intr\n"));
+                               D(printf("signal intr %d eol=%d\n",
+                                       len, ctrl->channels[c].current_d.eol));
                                ctrl->channels[c].regs[R_INTR] |= (1 << 2);
                                channel_update_irq(ctrl, c);
                        }
                                ctrl->channels[c].regs[R_INTR] |= (1 << 2);
                                channel_update_irq(ctrl, c);
                        }
+                       channel_store_d(ctrl, c);
                        if (ctrl->channels[c].current_d.eol) {
                                D(printf("channel %d EOL\n", c));
                                ctrl->channels[c].eol = 1;
                        if (ctrl->channels[c].current_d.eol) {
                                D(printf("channel %d EOL\n", c));
                                ctrl->channels[c].eol = 1;
@@ -460,13 +467,13 @@ static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
                                        ctrl->channels[c].current_d.buf;
                        }
 
                                        ctrl->channels[c].current_d.buf;
                        }
 
-                       channel_store_d(ctrl, c);
                        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
                                                        saved_data_buf;
                        D(dump_d(c, &ctrl->channels[c].current_d));
                }
                ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
                        ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
                                                        saved_data_buf;
                        D(dump_d(c, &ctrl->channels[c].current_d));
                }
                ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
-       }
+       } while (!ctrl->channels[c].eol);
+       return 1;
 }
 
 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, 
 }
 
 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, 
@@ -478,6 +485,7 @@ static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
        if (ctrl->channels[c].eol == 1)
                return 0;
 
        if (ctrl->channels[c].eol == 1)
                return 0;
 
+       channel_load_d(ctrl, c);
        saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
        len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
        len -= saved_data_buf;
        saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
        len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
        len -= saved_data_buf;
@@ -496,8 +504,7 @@ static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
                D(printf("in dscr end len=%d\n", 
                         ctrl->channels[c].current_d.after
                         - ctrl->channels[c].current_d.buf));
                D(printf("in dscr end len=%d\n", 
                         ctrl->channels[c].current_d.after
                         - ctrl->channels[c].current_d.buf));
-               ctrl->channels[c].current_d.after = 
-                       (void *)(unsigned long) saved_data_buf;
+               ctrl->channels[c].current_d.after = saved_data_buf;
 
                /* Done. Step to next.  */
                if (ctrl->channels[c].current_d.intr) {
 
                /* Done. Step to next.  */
                if (ctrl->channels[c].current_d.intr) {
@@ -539,19 +546,19 @@ static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
        return len;
 }
 
        return len;
 }
 
-static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c)
+static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
 {
 {
-       if (ctrl->channels[c].client->client.pull)
+       if (ctrl->channels[c].client->client.pull) {
                ctrl->channels[c].client->client.pull(
                        ctrl->channels[c].client->client.opaque);
                ctrl->channels[c].client->client.pull(
                        ctrl->channels[c].client->client.opaque);
+               return 1;
+       } else
+               return 0;
 }
 
 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
 {
 }
 
 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
 {
-        struct fs_dma_ctrl *ctrl = opaque;
-        CPUState *env = ctrl->env;
-        cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
-                  addr);
+        hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
         return 0;
 }
 
         return 0;
 }
 
@@ -562,9 +569,10 @@ dma_readl (void *opaque, target_phys_addr_t addr)
        int c;
        uint32_t r = 0;
 
        int c;
        uint32_t r = 0;
 
-       /* Make addr relative to this instances base.  */
-       c = fs_channel(ctrl->base, addr);
-       addr &= 0x1fff;
+       /* Make addr relative to this channel and bounded to nr regs.  */
+       c = fs_channel(addr);
+       addr &= 0xff;
+       addr >>= 2;
        switch (addr)
        {
                case RW_STAT:
        switch (addr)
        {
                case RW_STAT:
@@ -575,7 +583,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
 
                default:
                        r = ctrl->channels[c].regs[addr];
 
                default:
                        r = ctrl->channels[c].regs[addr];
-                       D(printf ("%s c=%d addr=%x\n",
+                       D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
                                  __func__, c, addr));
                        break;
        }
                                  __func__, c, addr));
                        break;
        }
@@ -585,10 +593,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
 static void
 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
 static void
 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
-        struct fs_dma_ctrl *ctrl = opaque;
-        CPUState *env = ctrl->env;
-        cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
-                  addr);
+        hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
 }
 
 static void
 }
 
 static void
@@ -608,9 +613,10 @@ dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
         struct fs_dma_ctrl *ctrl = opaque;
        int c;
 
         struct fs_dma_ctrl *ctrl = opaque;
        int c;
 
-        /* Make addr relative to this instances base.  */
-       c = fs_channel(ctrl->base, addr);
-        addr &= 0x1fff;
+        /* Make addr relative to this channel and bounded to nr regs.  */
+       c = fs_channel(addr);
+        addr &= 0xff;
+        addr >>= 2;
         switch (addr)
        {
                case RW_DATA:
         switch (addr)
        {
                case RW_DATA:
@@ -656,24 +662,25 @@ dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
                        break;
 
                default:
                        break;
 
                default:
-                       D(printf ("%s c=%d %x %x\n", __func__, c, addr));
+                       D(printf ("%s c=%d " TARGET_FMT_plx "\n",
+                               __func__, c, addr));
                        break;
         }
 }
 
                        break;
         }
 }
 
-static CPUReadMemoryFunc *dma_read[] = {
+static CPUReadMemoryFunc * const dma_read[] = {
        &dma_rinvalid,
        &dma_rinvalid,
        &dma_readl,
 };
 
        &dma_rinvalid,
        &dma_rinvalid,
        &dma_readl,
 };
 
-static CPUWriteMemoryFunc *dma_write[] = {
+static CPUWriteMemoryFunc * const dma_write[] = {
        &dma_winvalid,
        &dma_winvalid,
        &dma_writel,
 };
 
        &dma_winvalid,
        &dma_winvalid,
        &dma_writel,
 };
 
-void etraxfs_dmac_run(void *opaque)
+static int etraxfs_dmac_run(void *opaque)
 {
        struct fs_dma_ctrl *ctrl = opaque;
        int i;
 {
        struct fs_dma_ctrl *ctrl = opaque;
        int i;
@@ -685,13 +692,14 @@ void etraxfs_dmac_run(void *opaque)
        {
                if (ctrl->channels[i].state == RUNNING)
                {
        {
                if (ctrl->channels[i].state == RUNNING)
                {
-                       p++;
-                       if (ctrl->channels[i].input)
-                               channel_in_run(ctrl, i);
-                       else
-                               channel_out_run(ctrl, i);
+                       if (ctrl->channels[i].input) {
+                               p += channel_in_run(ctrl, i);
+                       } else {
+                               p += channel_out_run(ctrl, i);
+                       }
                }
        }
                }
        }
+       return p;
 }
 
 int etraxfs_dmac_input(struct etraxfs_dma_client *client, 
 }
 
 int etraxfs_dmac_input(struct etraxfs_dma_client *client, 
@@ -705,7 +713,7 @@ int etraxfs_dmac_input(struct etraxfs_dma_client *client,
 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
 {
        struct fs_dma_ctrl *ctrl = opaque;
 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
 {
        struct fs_dma_ctrl *ctrl = opaque;
-       ctrl->channels[c].irq = line;
+       ctrl->channels[c].irq = *line;
        ctrl->channels[c].input = input;
 }
 
        ctrl->channels[c].input = input;
 }
 
@@ -722,45 +730,27 @@ void etraxfs_dmac_connect_client(void *opaque, int c,
 static void DMA_run(void *opaque)
 {
     struct fs_dma_ctrl *etraxfs_dmac = opaque;
 static void DMA_run(void *opaque)
 {
     struct fs_dma_ctrl *etraxfs_dmac = opaque;
+    int p = 1;
+
     if (vm_running)
     if (vm_running)
-        etraxfs_dmac_run(etraxfs_dmac);
-    qemu_bh_schedule_idle(etraxfs_dmac->bh);
+        p = etraxfs_dmac_run(etraxfs_dmac);
+
+    if (p)
+        qemu_bh_schedule_idle(etraxfs_dmac->bh);
 }
 
 }
 
-void *etraxfs_dmac_init(CPUState *env, 
-                       target_phys_addr_t base, int nr_channels)
+void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
 {
        struct fs_dma_ctrl *ctrl = NULL;
 {
        struct fs_dma_ctrl *ctrl = NULL;
-       int i;
 
        ctrl = qemu_mallocz(sizeof *ctrl);
 
        ctrl = qemu_mallocz(sizeof *ctrl);
-       if (!ctrl)
-               return NULL;
 
         ctrl->bh = qemu_bh_new(DMA_run, ctrl);
 
         ctrl->bh = qemu_bh_new(DMA_run, ctrl);
-        qemu_bh_schedule_idle(ctrl->bh);
 
 
-       ctrl->base = base;
-       ctrl->env = env;
        ctrl->nr_channels = nr_channels;
        ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
        ctrl->nr_channels = nr_channels;
        ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
-       if (!ctrl->channels)
-               goto err;
-
-       for (i = 0; i < nr_channels; i++)
-       {
-               ctrl->channels[i].regmap = cpu_register_io_memory(0,
-                                                                 dma_read, 
-                                                                 dma_write, 
-                                                                 ctrl);
-               cpu_register_physical_memory (base + i * 0x2000,
-                                             sizeof ctrl->channels[i].regs, 
-                                             ctrl->channels[i].regmap);
-       }
 
 
+       ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl, DEVICE_NATIVE_ENDIAN);
+       cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
        return ctrl;
        return ctrl;
-  err:
-       qemu_free(ctrl->channels);
-       qemu_free(ctrl);
-       return NULL;
 }
 }
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