Merge remote-tracking branch 'remotes/kraxel/tags/usb-20170717-pull-request' into...

[qemu.git] / hw / char / pl011.c

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index ebec64f9525f7f8b20cf537c0cfe9240cc214925..2aa277fc4f25bd3a091d7970fb6edb579b3bb8a9 100644 (file)
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -7,15 +7,23 @@
  * This code is licensed under the GPL.
  */
 
  * This code is licensed under the GPL.
  */
 

+#include "qemu/osdep.h"

 #include "hw/sysbus.h"
 #include "hw/sysbus.h"

-#include "sysemu/char.h"
+#include "chardev/char-fe.h"
+#include "qemu/log.h"
+#include "trace.h"
+
+#define TYPE_PL011 "pl011"
+#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
+
+typedef struct PL011State {
+    SysBusDevice parent_obj;

 
 

-typedef struct {
-    SysBusDevice busdev;

     MemoryRegion iomem;
     uint32_t readbuff;
     uint32_t flags;
     uint32_t lcr;
     MemoryRegion iomem;
     uint32_t readbuff;
     uint32_t flags;
     uint32_t lcr;

+    uint32_t rsr;

     uint32_t cr;
     uint32_t dmacr;
     uint32_t int_enabled;
     uint32_t cr;
     uint32_t dmacr;
     uint32_t int_enabled;


@@ -28,10 +36,10 @@ typedef struct {
     int read_pos;
     int read_count;
     int read_trigger;
     int read_pos;
     int read_count;
     int read_trigger;

-    CharDriverState *chr;
+    CharBackend chr;

     qemu_irq irq;
     const unsigned char *id;
     qemu_irq irq;
     const unsigned char *id;

-} pl011_state;
+} PL011State;

 
 #define PL011_INT_TX 0x20
 #define PL011_INT_RX 0x10
 
 #define PL011_INT_TX 0x20
 #define PL011_INT_RX 0x10


@@ -46,23 +54,22 @@ static const unsigned char pl011_id_arm[8] =
 static const unsigned char pl011_id_luminary[8] =
   { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
 
 static const unsigned char pl011_id_luminary[8] =
   { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
 

-static void pl011_update(pl011_state *s)
+static void pl011_update(PL011State *s)

 {
     uint32_t flags;
 
     flags = s->int_level & s->int_enabled;
 {
     uint32_t flags;
 
     flags = s->int_level & s->int_enabled;

+    trace_pl011_irq_state(flags != 0);

     qemu_set_irq(s->irq, flags != 0);
 }
 
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
     qemu_set_irq(s->irq, flags != 0);
 }
 
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {

-    pl011_state *s = (pl011_state *)opaque;
+    PL011State *s = (PL011State *)opaque;

     uint32_t c;
     uint32_t c;

+    uint64_t r;

 
 

-    if (offset >= 0xfe0 && offset < 0x1000) {
-        return s->id[(offset - 0xfe0) >> 2];
-    }

     switch (offset >> 2) {
     case 0: /* UARTDR */
         s->flags &= ~PL011_FLAG_RXFF;
     switch (offset >> 2) {
     case 0: /* UARTDR */
         s->flags &= ~PL011_FLAG_RXFF;


@@ -77,43 +84,63 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
         }
         if (s->read_count == s->read_trigger - 1)
             s->int_level &= ~ PL011_INT_RX;
         }
         if (s->read_count == s->read_trigger - 1)
             s->int_level &= ~ PL011_INT_RX;

+        trace_pl011_read_fifo(s->read_count);
+        s->rsr = c >> 8;

         pl011_update(s);
         pl011_update(s);

-        if (s->chr) {
-            qemu_chr_accept_input(s->chr);
-        }
-        return c;
-    case 1: /* UARTCR */
-        return 0;
+        qemu_chr_fe_accept_input(&s->chr);
+        r = c;
+        break;
+    case 1: /* UARTRSR */
+        r = s->rsr;
+        break;

     case 6: /* UARTFR */
     case 6: /* UARTFR */

-        return s->flags;
+        r = s->flags;
+        break;

     case 8: /* UARTILPR */
     case 8: /* UARTILPR */

-        return s->ilpr;
+        r = s->ilpr;
+        break;

     case 9: /* UARTIBRD */
     case 9: /* UARTIBRD */

-        return s->ibrd;
+        r = s->ibrd;
+        break;

     case 10: /* UARTFBRD */
     case 10: /* UARTFBRD */

-        return s->fbrd;
+        r = s->fbrd;
+        break;

     case 11: /* UARTLCR_H */
     case 11: /* UARTLCR_H */

-        return s->lcr;
+        r = s->lcr;
+        break;

     case 12: /* UARTCR */
     case 12: /* UARTCR */

-        return s->cr;
+        r = s->cr;
+        break;

     case 13: /* UARTIFLS */
     case 13: /* UARTIFLS */

-        return s->ifl;
+        r = s->ifl;
+        break;

     case 14: /* UARTIMSC */
     case 14: /* UARTIMSC */

-        return s->int_enabled;
+        r = s->int_enabled;
+        break;

     case 15: /* UARTRIS */
     case 15: /* UARTRIS */

-        return s->int_level;
+        r = s->int_level;
+        break;

     case 16: /* UARTMIS */
     case 16: /* UARTMIS */

-        return s->int_level & s->int_enabled;
+        r = s->int_level & s->int_enabled;
+        break;

     case 18: /* UARTDMACR */
     case 18: /* UARTDMACR */

-        return s->dmacr;
+        r = s->dmacr;
+        break;
+    case 0x3f8 ... 0x400:
+        r = s->id[(offset - 0xfe0) >> 2];
+        break;

     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "pl011_read: Bad offset %x\n", (int)offset);
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "pl011_read: Bad offset %x\n", (int)offset);

-        return 0;
+        r = 0;
+        break;

     }
     }

+
+    trace_pl011_read(offset, r);
+    return r;

 }
 
 }
 

-static void pl011_set_read_trigger(pl011_state *s)
+static void pl011_set_read_trigger(PL011State *s)

 {
 #if 0
     /* The docs say the RX interrupt is triggered when the FIFO exceeds
 {
 #if 0
     /* The docs say the RX interrupt is triggered when the FIFO exceeds


@@ -130,20 +157,23 @@ static void pl011_set_read_trigger(pl011_state *s)
 static void pl011_write(void *opaque, hwaddr offset,
                         uint64_t value, unsigned size)
 {
 static void pl011_write(void *opaque, hwaddr offset,
                         uint64_t value, unsigned size)
 {

-    pl011_state *s = (pl011_state *)opaque;
+    PL011State *s = (PL011State *)opaque;

     unsigned char ch;
 
     unsigned char ch;
 

+    trace_pl011_write(offset, value);
+

     switch (offset >> 2) {
     case 0: /* UARTDR */
         /* ??? Check if transmitter is enabled.  */
         ch = value;
     switch (offset >> 2) {
     case 0: /* UARTDR */
         /* ??? Check if transmitter is enabled.  */
         ch = value;

-        if (s->chr)
-            qemu_chr_fe_write(s->chr, &ch, 1);
+        /* XXX this blocks entire thread. Rewrite to use
+         * qemu_chr_fe_write and background I/O callbacks */
+        qemu_chr_fe_write_all(&s->chr, &ch, 1);

         s->int_level |= PL011_INT_TX;
         pl011_update(s);
         break;
         s->int_level |= PL011_INT_TX;
         pl011_update(s);
         break;

-    case 1: /* UARTCR */
-        s->cr = value;
+    case 1: /* UARTRSR/UARTECR */
+        s->rsr = 0;

         break;
     case 6: /* UARTFR */
         /* Writes to Flag register are ignored.  */
         break;
     case 6: /* UARTFR */
         /* Writes to Flag register are ignored.  */


@@ -158,6 +188,11 @@ static void pl011_write(void *opaque, hwaddr offset,
         s->fbrd = value;
         break;
     case 11: /* UARTLCR_H */
         s->fbrd = value;
         break;
     case 11: /* UARTLCR_H */

+        /* Reset the FIFO state on FIFO enable or disable */
+        if ((s->lcr ^ value) & 0x10) {
+            s->read_count = 0;
+            s->read_pos = 0;
+        }

         s->lcr = value;
         pl011_set_read_trigger(s);
         break;
         s->lcr = value;
         pl011_set_read_trigger(s);
         break;


@@ -191,17 +226,21 @@ static void pl011_write(void *opaque, hwaddr offset,
 
 static int pl011_can_receive(void *opaque)
 {
 
 static int pl011_can_receive(void *opaque)
 {

-    pl011_state *s = (pl011_state *)opaque;
+    PL011State *s = (PL011State *)opaque;
+    int r;

 
 

-    if (s->lcr & 0x10)
-        return s->read_count < 16;
-    else
-        return s->read_count < 1;
+    if (s->lcr & 0x10) {
+        r = s->read_count < 16;
+    } else {
+        r = s->read_count < 1;
+    }
+    trace_pl011_can_receive(s->lcr, s->read_count, r);
+    return r;

 }
 
 static void pl011_put_fifo(void *opaque, uint32_t value)
 {
 }
 
 static void pl011_put_fifo(void *opaque, uint32_t value)
 {

-    pl011_state *s = (pl011_state *)opaque;
+    PL011State *s = (PL011State *)opaque;

     int slot;
 
     slot = s->read_pos + s->read_count;
     int slot;
 
     slot = s->read_pos + s->read_count;


@@ -210,7 +249,9 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
     s->read_fifo[slot] = value;
     s->read_count++;
     s->flags &= ~PL011_FLAG_RXFE;
     s->read_fifo[slot] = value;
     s->read_count++;
     s->flags &= ~PL011_FLAG_RXFE;

-    if (s->cr & 0x10 || s->read_count == 16) {
+    trace_pl011_put_fifo(value, s->read_count);
+    if (!(s->lcr & 0x10) || s->read_count == 16) {
+        trace_pl011_put_fifo_full();

         s->flags |= PL011_FLAG_RXFF;
     }
     if (s->read_count == s->read_trigger) {
         s->flags |= PL011_FLAG_RXFF;
     }
     if (s->read_count == s->read_trigger) {


@@ -238,87 +279,87 @@ static const MemoryRegionOps pl011_ops = {
 
 static const VMStateDescription vmstate_pl011 = {
     .name = "pl011",
 
 static const VMStateDescription vmstate_pl011 = {
     .name = "pl011",

-    .version_id = 1,
-    .minimum_version_id = 1,
-    .minimum_version_id_old = 1,
-    .fields      = (VMStateField[]) {
-        VMSTATE_UINT32(readbuff, pl011_state),
-        VMSTATE_UINT32(flags, pl011_state),
-        VMSTATE_UINT32(lcr, pl011_state),
-        VMSTATE_UINT32(cr, pl011_state),
-        VMSTATE_UINT32(dmacr, pl011_state),
-        VMSTATE_UINT32(int_enabled, pl011_state),
-        VMSTATE_UINT32(int_level, pl011_state),
-        VMSTATE_UINT32_ARRAY(read_fifo, pl011_state, 16),
-        VMSTATE_UINT32(ilpr, pl011_state),
-        VMSTATE_UINT32(ibrd, pl011_state),
-        VMSTATE_UINT32(fbrd, pl011_state),
-        VMSTATE_UINT32(ifl, pl011_state),
-        VMSTATE_INT32(read_pos, pl011_state),
-        VMSTATE_INT32(read_count, pl011_state),
-        VMSTATE_INT32(read_trigger, pl011_state),
+    .version_id = 2,
+    .minimum_version_id = 2,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(readbuff, PL011State),
+        VMSTATE_UINT32(flags, PL011State),
+        VMSTATE_UINT32(lcr, PL011State),
+        VMSTATE_UINT32(rsr, PL011State),
+        VMSTATE_UINT32(cr, PL011State),
+        VMSTATE_UINT32(dmacr, PL011State),
+        VMSTATE_UINT32(int_enabled, PL011State),
+        VMSTATE_UINT32(int_level, PL011State),
+        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
+        VMSTATE_UINT32(ilpr, PL011State),
+        VMSTATE_UINT32(ibrd, PL011State),
+        VMSTATE_UINT32(fbrd, PL011State),
+        VMSTATE_UINT32(ifl, PL011State),
+        VMSTATE_INT32(read_pos, PL011State),
+        VMSTATE_INT32(read_count, PL011State),
+        VMSTATE_INT32(read_trigger, PL011State),

         VMSTATE_END_OF_LIST()
     }
 };
 
         VMSTATE_END_OF_LIST()
     }
 };
 

-static int pl011_init(SysBusDevice *dev, const unsigned char *id)
+static Property pl011_properties[] = {
+    DEFINE_PROP_CHR("chardev", PL011State, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pl011_init(Object *obj)

 {
 {

-    pl011_state *s = FROM_SYSBUS(pl011_state, dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    PL011State *s = PL011(obj);

 
     memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
 
     memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);

-    sysbus_init_mmio(dev, &s->iomem);
-    sysbus_init_irq(dev, &s->irq);
-    s->id = id;
-    s->chr = qemu_char_get_next_serial();
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(sbd, &s->irq);

 
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
     s->flags = 0x90;
 
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
     s->flags = 0x90;

-    if (s->chr) {
-        qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
-                              pl011_event, s);
-    }
-    vmstate_register(&dev->qdev, -1, &vmstate_pl011, s);
-    return 0;
-}

 
 

-static int pl011_arm_init(SysBusDevice *dev)
-{
-    return pl011_init(dev, pl011_id_arm);
+    s->id = pl011_id_arm;

 }
 
 }
 

-static int pl011_luminary_init(SysBusDevice *dev)
+static void pl011_realize(DeviceState *dev, Error **errp)

 {
 {

-    return pl011_init(dev, pl011_id_luminary);
+    PL011State *s = PL011(dev);
+
+    qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
+                             pl011_event, NULL, s, NULL, true);

 }
 
 }
 

-static void pl011_arm_class_init(ObjectClass *klass, void *data)
+static void pl011_class_init(ObjectClass *oc, void *data)

 {
 {

-    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(oc);

 
 

-    sdc->init = pl011_arm_init;
+    dc->realize = pl011_realize;
+    dc->vmsd = &vmstate_pl011;
+    dc->props = pl011_properties;

 }
 
 static const TypeInfo pl011_arm_info = {
 }
 
 static const TypeInfo pl011_arm_info = {

-    .name          = "pl011",
+    .name          = TYPE_PL011,

     .parent        = TYPE_SYS_BUS_DEVICE,
     .parent        = TYPE_SYS_BUS_DEVICE,

-    .instance_size = sizeof(pl011_state),
-    .class_init    = pl011_arm_class_init,
+    .instance_size = sizeof(PL011State),
+    .instance_init = pl011_init,
+    .class_init    = pl011_class_init,

 };
 
 };
 

-static void pl011_luminary_class_init(ObjectClass *klass, void *data)
+static void pl011_luminary_init(Object *obj)

 {
 {

-    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+    PL011State *s = PL011(obj);

 
 

-    sdc->init = pl011_luminary_init;
+    s->id = pl011_id_luminary;

 }
 
 static const TypeInfo pl011_luminary_info = {
     .name          = "pl011_luminary",
 }
 
 static const TypeInfo pl011_luminary_info = {
     .name          = "pl011_luminary",

-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(pl011_state),
-    .class_init    = pl011_luminary_class_init,
+    .parent        = TYPE_PL011,
+    .instance_init = pl011_luminary_init,

 };
 
 static void pl011_register_types(void)
 };
 
 static void pl011_register_types(void)