#include "hw.h"
#include "pc.h"
#include "pci.h"
+#include "pci_host.h"
#include "isa.h"
#include "sysbus.h"
+#include "range.h"
-typedef uint32_t pci_addr_t;
-#include "pci_host.h"
+/*
+ * I440FX chipset data sheet.
+ * http://download.intel.com/design/chipsets/datashts/29054901.pdf
+ */
typedef PCIHostState I440FXState;
typedef struct PIIX3State {
PCIDevice dev;
int pci_irq_levels[4];
-} PIIX3State;
-
-typedef struct PIIX3IrqState {
- PIIX3State *piix3;
qemu_irq *pic;
-} PIIX3IrqState;
+} PIIX3State;
struct PCII440FXState {
PCIDevice dev;
target_phys_addr_t isa_page_descs[384 / 4];
uint8_t smm_enabled;
- PIIX3IrqState *irq_state;
+ PIIX3State *piix3;
};
-static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
-{
- I440FXState *s = opaque;
- s->config_reg = val;
-}
-static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
-{
- I440FXState *s = opaque;
- return s->config_reg;
-}
+#define I440FX_PAM 0x59
+#define I440FX_PAM_SIZE 7
+#define I440FX_SMRAM 0x72
static void piix3_set_irq(void *opaque, int irq_num, int level);
int i, r;
uint32_t smram, addr;
- update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
+ update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
for(i = 0; i < 12; i++) {
- r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
+ r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
}
- smram = d->dev.config[0x72];
+ smram = d->dev.config[I440FX_SMRAM];
if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
} else {
}
}
-void i440fx_set_smm(PCII440FXState *d, int val)
+static void i440fx_set_smm(int val, void *arg)
{
+ PCII440FXState *d = arg;
+
val = (val != 0);
if (d->smm_enabled != val) {
d->smm_enabled = val;
/* XXX: implement SMRAM.D_LOCK */
pci_default_write_config(dev, address, val, len);
- if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
+ if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
+ range_covers_byte(address, len, I440FX_SMRAM)) {
i440fx_update_memory_mappings(d);
+ }
}
static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
if (version_id == 2)
for (i = 0; i < 4; i++)
- d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
+ d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
return 0;
}
{
I440FXState *s = FROM_SYSBUS(I440FXState, dev);
- register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
- register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
+ pci_host_conf_register_ioport(0xcf8, s);
- register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
- register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
- register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
- register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
- register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
- register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
+ pci_host_data_register_ioport(0xcfc, s);
return 0;
}
pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
d->dev.config[0x08] = 0x02; // revision
pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
- d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
- d->dev.config[0x72] = 0x02; /* SMRAM */
+ d->dev.config[I440FX_SMRAM] = 0x02;
- vmstate_register(0, &vmstate_i440fx, d);
+ cpu_smm_register(&i440fx_set_smm, d);
return 0;
}
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
{
DeviceState *dev;
PCIBus *b;
PCIDevice *d;
I440FXState *s;
- PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));
+ PIIX3State *piix3;
- irq_state->pic = pic;
dev = qdev_create(NULL, "i440FX-pcihost");
s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
- b = pci_register_bus(&s->busdev.qdev, "pci.0",
- piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
+ b = pci_bus_new(&s->busdev.qdev, NULL, 0);
s->bus = b;
- qdev_init(dev);
+ qdev_init_nofail(dev);
d = pci_create_simple(b, 0, "i440FX");
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
- (*pi440fx_state)->irq_state = irq_state;
- irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
- pci_create_simple(b, -1, "PIIX3"));
- *piix3_devfn = irq_state->piix3->dev.devfn;
+ piix3 = DO_UPCAST(PIIX3State, dev,
+ pci_create_simple_multifunction(b, -1, true, "PIIX3"));
+ piix3->pic = pic;
+ pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
+ (*pi440fx_state)->piix3 = piix3;
+
+ *piix3_devfn = piix3->dev.devfn;
+
+ ram_size = ram_size / 8 / 1024 / 1024;
+ if (ram_size > 255)
+ ram_size = 255;
+ (*pi440fx_state)->dev.config[0x57]=ram_size;
return b;
}
static void piix3_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
- PIIX3IrqState *irq_state = opaque;
+ PIIX3State *piix3 = opaque;
- irq_state->piix3->pci_irq_levels[irq_num] = level;
+ piix3->pci_irq_levels[irq_num] = level;
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
+ pic_irq = piix3->dev.config[0x60 + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped
to it */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
- pic_level |= irq_state->piix3->pci_irq_levels[i];
+ if (pic_irq == piix3->dev.config[0x60 + i])
+ pic_level |= piix3->pci_irq_levels[i];
}
- qemu_set_irq(irq_state->pic[pic_irq], pic_level);
+ qemu_set_irq(piix3->pic[pic_irq], pic_level);
}
}
uint8_t *pci_conf;
isa_bus_new(&d->dev.qdev);
- vmstate_register(0, &vmstate_piix3, d);
pci_conf = d->dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
- pci_conf[PCI_HEADER_TYPE] =
- PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
- piix3_reset(d);
qemu_register_reset(piix3_reset, d);
return 0;
}
.qdev.name = "i440FX",
.qdev.desc = "Host bridge",
.qdev.size = sizeof(PCII440FXState),
+ .qdev.vmsd = &vmstate_i440fx,
.qdev.no_user = 1,
+ .no_hotplug = 1,
.init = i440fx_initfn,
.config_write = i440fx_write_config,
},{
.qdev.name = "PIIX3",
.qdev.desc = "ISA bridge",
.qdev.size = sizeof(PIIX3State),
+ .qdev.vmsd = &vmstate_piix3,
.qdev.no_user = 1,
+ .no_hotplug = 1,
.init = piix3_initfn,
},{
/* end of list */
static SysBusDeviceInfo i440fx_pcihost_info = {
.init = i440fx_pcihost_initfn,
.qdev.name = "i440FX-pcihost",
+ .qdev.fw_name = "pci",
.qdev.size = sizeof(I440FXState),
.qdev.no_user = 1,
};
projects / qemu.git / blobdiff