* THE SOFTWARE.
*/
#include "hw/sysbus.h"
+#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "hw/sparc/sun4m.h"
#include "hw/timer/m48t59.h"
#include "hw/empty_slot.h"
#include "hw/loader.h"
#include "elf.h"
-#include "sysemu/blockdev.h"
+#include "sysemu/block-backend.h"
#include "trace.h"
/*
{
}
-static int fw_cfg_boot_set(void *opaque, const char *boot_device)
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
{
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
- return 0;
}
-static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
+static void nvram_init(Nvram *nvram, uint8_t *macaddr,
const char *cmdline, const char *boot_devices,
ram_addr_t RAM_size, uint32_t kernel_size,
int width, int height, int depth,
uint32_t start, end;
uint8_t image[0x1ff0];
struct OpenBIOS_nvpart_v1 *part_header;
+ NvramClass *k = NVRAM_GET_CLASS(nvram);
memset(image, '\0', sizeof(image));
Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
nvram_machine_id);
- for (i = 0; i < sizeof(image); i++)
- m48t59_write(nvram, i, image[i]);
+ for (i = 0; i < sizeof(image); i++) {
+ (k->write)(nvram, i, image[i]);
+ }
}
static DeviceState *slavio_intctl;
-void sun4m_pic_info(Monitor *mon, const QDict *qdict)
+void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict)
{
if (slavio_intctl)
slavio_pic_info(mon, slavio_intctl);
}
-void sun4m_irq_info(Monitor *mon, const QDict *qdict)
+void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict)
{
if (slavio_intctl)
slavio_irq_info(mon, slavio_intctl);
sysbus_connect_irq(s, 0, cpu_halt);
}
-static void tcx_init(hwaddr addr, int vram_size, int width,
+static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
int height, int depth)
{
DeviceState *dev;
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
+ qdev_prop_set_uint64(dev, "prom_addr", addr);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
- /* 8-bit plane */
- sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
- /* DAC */
- sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
- /* TEC (dummy) */
- sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
- /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
- sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
- if (depth == 24) {
- /* 24-bit plane */
- sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
- /* Control plane */
- sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
+
+ /* 10/ROM : FCode ROM */
+ sysbus_mmio_map(s, 0, addr);
+ /* 2/STIP : Stipple */
+ sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
+ /* 3/BLIT : Blitter */
+ sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
+ /* 5/RSTIP : Raw Stipple */
+ sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
+ /* 6/RBLIT : Raw Blitter */
+ sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
+ /* 7/TEC : Transform Engine */
+ sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
+ /* 8/CMAP : DAC */
+ sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
+ /* 9/THC : */
+ if (depth == 8) {
+ sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
} else {
- /* THC 8 bit (dummy) */
- sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
+ sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
+ }
+ /* 11/DHC : */
+ sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
+ /* 12/ALT : */
+ sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
+ /* 0/DFB8 : 8-bit plane */
+ sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
+ /* 1/DFB24 : 24bit plane */
+ sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
+ /* 4/RDFB32: Raw framebuffer. Control plane */
+ sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
+ /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
+ if (depth == 8) {
+ sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
}
+
+ sysbus_connect_irq(s, 0, irq);
+}
+
+static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
+ int height, int depth)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ dev = qdev_create(NULL, "cgthree");
+ qdev_prop_set_uint32(dev, "vram-size", vram_size);
+ qdev_prop_set_uint16(dev, "width", width);
+ qdev_prop_set_uint16(dev, "height", height);
+ qdev_prop_set_uint16(dev, "depth", depth);
+ qdev_prop_set_uint64(dev, "prom-addr", addr);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+
+ /* FCode ROM */
+ sysbus_mmio_map(s, 0, addr);
+ /* DAC */
+ sysbus_mmio_map(s, 1, addr + 0x400000ULL);
+ /* 8-bit plane */
+ sysbus_mmio_map(s, 2, addr + 0x800000ULL);
+
+ sysbus_connect_irq(s, 0, irq);
}
/* NCR89C100/MACIO Internal ID register */
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
- cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+ cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
IDRegState *s = MACIO_ID_REGISTER(dev);
memory_region_init_ram(&s->mem, OBJECT(s),
- "sun4m.idreg", sizeof(idreg_data));
+ "sun4m.idreg", sizeof(idreg_data), &error_abort);
vmstate_register_ram_global(&s->mem);
memory_region_set_readonly(&s->mem, true);
sysbus_init_mmio(dev, &s->mem);
{
AFXState *s = TCX_AFX(dev);
- memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4);
+ memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_abort);
vmstate_register_ram_global(&s->mem);
sysbus_init_mmio(dev, &s->mem);
return 0;
{
PROMState *s = OPENPROM(dev);
- memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX);
+ memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
+ &error_abort);
vmstate_register_ram_global(&s->prom);
memory_region_set_readonly(&s->prom, true);
sysbus_init_mmio(dev, &s->prom);
{
RamDevice *d = SUN4M_RAM(dev);
- memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size);
+ memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size,
+ &error_abort);
vmstate_register_ram_global(&d->ram);
sysbus_init_mmio(dev, &d->ram);
return 0;
}
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
- QEMUMachineInitArgs *args)
+ MachineState *machine)
{
- const char *cpu_model = args->cpu_model;
+ const char *cpu_model = machine->cpu_model;
unsigned int i;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
/* set up devices */
- ram_init(0, args->ram_size, hwdef->max_mem);
+ ram_init(0, machine->ram_size, hwdef->max_mem);
/* models without ECC don't trap when missing ram is accessed */
if (!hwdef->ecc_base) {
- empty_slot_init(args->ram_size, hwdef->max_mem - args->ram_size);
+ empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
}
prom_init(hwdef->slavio_base, bios_name);
slavio_irq[16], iommu, &ledma_irq, 1);
if (graphic_depth != 8 && graphic_depth != 24) {
- fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
+ error_report("Unsupported depth: %d", graphic_depth);
exit (1);
}
num_vsimms = 0;
if (num_vsimms == 0) {
- tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
- graphic_depth);
+ if (vga_interface_type == VGA_CG3) {
+ if (graphic_depth != 8) {
+ error_report("Unsupported depth: %d", graphic_depth);
+ exit(1);
+ }
+
+ if (!(graphic_width == 1024 && graphic_height == 768) &&
+ !(graphic_width == 1152 && graphic_height == 900)) {
+ error_report("Unsupported resolution: %d x %d", graphic_width,
+ graphic_height);
+ exit(1);
+ }
+
+ /* sbus irq 5 */
+ cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
+ graphic_width, graphic_height, graphic_depth);
+ } else {
+ /* If no display specified, default to TCX */
+ if (graphic_depth != 8 && graphic_depth != 24) {
+ error_report("Unsupported depth: %d", graphic_depth);
+ exit(1);
+ }
+
+ if (!(graphic_width == 1024 && graphic_height == 768)) {
+ error_report("Unsupported resolution: %d x %d",
+ graphic_width, graphic_height);
+ exit(1);
+ }
+
+ tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
+ graphic_width, graphic_height, graphic_depth);
+ }
}
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
- nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
+ nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
empty_slot_init(hwdef->bpp_base, 0x20);
}
- kernel_size = sun4m_load_kernel(args->kernel_filename,
- args->initrd_filename,
- args->ram_size);
+ kernel_size = sun4m_load_kernel(machine->kernel_filename,
+ machine->initrd_filename,
+ machine->ram_size);
- nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, args->kernel_cmdline,
- args->boot_device, args->ram_size, kernel_size, graphic_width,
- graphic_height, graphic_depth, hwdef->nvram_machine_id,
- "Sun4m");
+ nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
+ machine->boot_order, machine->ram_size, kernel_size,
+ graphic_width, graphic_height, graphic_depth,
+ hwdef->nvram_machine_id, "Sun4m");
if (hwdef->ecc_base)
ecc_init(hwdef->ecc_base, slavio_irq[28],
hwdef->ecc_version);
- fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
+ fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
- fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
- if (args->kernel_cmdline) {
+ if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
- args->kernel_cmdline);
- fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, args->kernel_cmdline);
+ machine->kernel_cmdline);
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
- strlen(args->kernel_cmdline) + 1);
+ strlen(machine->kernel_cmdline) + 1);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
- fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, args->boot_device[0]);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
};
/* SPARCstation 5 hardware initialisation */
-static void ss5_init(QEMUMachineInitArgs *args)
+static void ss5_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[0], args);
+ sun4m_hw_init(&sun4m_hwdefs[0], machine);
}
/* SPARCstation 10 hardware initialisation */
-static void ss10_init(QEMUMachineInitArgs *args)
+static void ss10_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[1], args);
+ sun4m_hw_init(&sun4m_hwdefs[1], machine);
}
/* SPARCserver 600MP hardware initialisation */
-static void ss600mp_init(QEMUMachineInitArgs *args)
+static void ss600mp_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[2], args);
+ sun4m_hw_init(&sun4m_hwdefs[2], machine);
}
/* SPARCstation 20 hardware initialisation */
-static void ss20_init(QEMUMachineInitArgs *args)
+static void ss20_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[3], args);
+ sun4m_hw_init(&sun4m_hwdefs[3], machine);
}
/* SPARCstation Voyager hardware initialisation */
-static void vger_init(QEMUMachineInitArgs *args)
+static void vger_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[4], args);
+ sun4m_hw_init(&sun4m_hwdefs[4], machine);
}
/* SPARCstation LX hardware initialisation */
-static void ss_lx_init(QEMUMachineInitArgs *args)
+static void ss_lx_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[5], args);
+ sun4m_hw_init(&sun4m_hwdefs[5], machine);
}
/* SPARCstation 4 hardware initialisation */
-static void ss4_init(QEMUMachineInitArgs *args)
+static void ss4_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[6], args);
+ sun4m_hw_init(&sun4m_hwdefs[6], machine);
}
/* SPARCClassic hardware initialisation */
-static void scls_init(QEMUMachineInitArgs *args)
+static void scls_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[7], args);
+ sun4m_hw_init(&sun4m_hwdefs[7], machine);
}
/* SPARCbook hardware initialisation */
-static void sbook_init(QEMUMachineInitArgs *args)
+static void sbook_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[8], args);
+ sun4m_hw_init(&sun4m_hwdefs[8], machine);
}
static QEMUMachine ss5_machine = {
.init = ss5_init,
.block_default_type = IF_SCSI,
.is_default = 1,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine ss10_machine = {
.init = ss10_init,
.block_default_type = IF_SCSI,
.max_cpus = 4,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine ss600mp_machine = {
.init = ss600mp_init,
.block_default_type = IF_SCSI,
.max_cpus = 4,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine ss20_machine = {
.init = ss20_init,
.block_default_type = IF_SCSI,
.max_cpus = 4,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine voyager_machine = {
.desc = "Sun4m platform, SPARCstation Voyager",
.init = vger_init,
.block_default_type = IF_SCSI,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine ss_lx_machine = {
.desc = "Sun4m platform, SPARCstation LX",
.init = ss_lx_init,
.block_default_type = IF_SCSI,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine ss4_machine = {
.desc = "Sun4m platform, SPARCstation 4",
.init = ss4_init,
.block_default_type = IF_SCSI,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine scls_machine = {
.desc = "Sun4m platform, SPARCClassic",
.init = scls_init,
.block_default_type = IF_SCSI,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static QEMUMachine sbook_machine = {
.desc = "Sun4m platform, SPARCbook",
.init = sbook_init,
.block_default_type = IF_SCSI,
- DEFAULT_MACHINE_OPTIONS,
+ .default_boot_order = "c",
};
static void sun4m_register_types(void)
projects / qemu.git / blobdiff