#include <signal.h>
#include "cpu.h"
-#include "exec-all.h"
-#include "hw/sh_intc.h"
+
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/sh4/sh_intc.h"
+#endif
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void superh_cpu_do_interrupt(CPUState *cs)
{
- env->exception_index = -1;
+ cs->exception_index = -1;
}
-int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
env->tea = address;
- env->exception_index = -1;
+ cs->exception_index = -1;
switch (rw) {
case 0:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
case 1:
- env->exception_index = 0x0c0;
+ cs->exception_index = 0x0c0;
break;
case 2:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
}
return 1;
#define MMU_DADDR_ERROR_READ (-12)
#define MMU_DADDR_ERROR_WRITE (-13)
-void do_interrupt(CPUState * env)
+void superh_cpu_do_interrupt(CPUState *cs)
{
- int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
- int do_exp, irq_vector = env->exception_index;
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+ int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
+ int do_exp, irq_vector = cs->exception_index;
/* prioritize exceptions over interrupts */
- do_exp = env->exception_index != -1;
- do_irq = do_irq && (env->exception_index == -1);
+ do_exp = cs->exception_index != -1;
+ do_irq = do_irq && (cs->exception_index == -1);
if (env->sr & SR_BL) {
- if (do_exp && env->exception_index != 0x1e0) {
- env->exception_index = 0x000; /* masked exception -> reset */
+ if (do_exp && cs->exception_index != 0x1e0) {
+ cs->exception_index = 0x000; /* masked exception -> reset */
}
- if (do_irq && !env->intr_at_halt) {
+ if (do_irq && !env->in_sleep) {
return; /* masked */
}
- env->intr_at_halt = 0;
}
+ env->in_sleep = 0;
if (do_irq) {
irq_vector = sh_intc_get_pending_vector(env->intc_handle,
if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *expname;
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case 0x0e0:
expname = "addr_error";
break;
}
qemu_log("exception 0x%03x [%s] raised\n",
irq_vector, expname);
- log_cpu_state(env, 0);
+ log_cpu_state(cs, 0);
}
env->ssr = env->sr;
env->flags = 0;
if (do_exp) {
- env->expevt = env->exception_index;
- switch (env->exception_index) {
+ env->expevt = cs->exception_index;
+ switch (cs->exception_index) {
case 0x000:
case 0x020:
case 0x140:
}
}
-static void update_itlb_use(CPUState * env, int itlbnb)
+static void update_itlb_use(CPUSH4State * env, int itlbnb)
{
uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
env->mmucr |= (or_mask << 24);
}
-static int itlb_replacement(CPUState * env)
+static int itlb_replacement(CPUSH4State * env)
{
- if ((env->mmucr & 0xe0000000) == 0xe0000000)
+ SuperHCPU *cpu = sh_env_get_cpu(env);
+
+ if ((env->mmucr & 0xe0000000) == 0xe0000000) {
return 0;
- if ((env->mmucr & 0x98000000) == 0x18000000)
+ }
+ if ((env->mmucr & 0x98000000) == 0x18000000) {
return 1;
- if ((env->mmucr & 0x54000000) == 0x04000000)
+ }
+ if ((env->mmucr & 0x54000000) == 0x04000000) {
return 2;
- if ((env->mmucr & 0x2c000000) == 0x00000000)
+ }
+ if ((env->mmucr & 0x2c000000) == 0x00000000) {
return 3;
- cpu_abort(env, "Unhandled itlb_replacement");
+ }
+ cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
-static int find_tlb_entry(CPUState * env, target_ulong address,
+static int find_tlb_entry(CPUSH4State * env, target_ulong address,
tlb_t * entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
return match;
}
-static void increment_urc(CPUState * env)
+static void increment_urc(CPUSH4State * env)
{
uint8_t urb, urc;
/* Copy and utlb entry into itlb
Return entry
*/
-static int copy_utlb_entry_itlb(CPUState *env, int utlb)
+static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
{
int itlb;
itlb = itlb_replacement(env);
ientry = &env->itlb[itlb];
if (ientry->v) {
- tlb_flush_page(env, ientry->vpn << 10);
+ tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
}
*ientry = env->utlb[utlb];
update_itlb_use(env, itlb);
/* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/
-static int find_itlb_entry(CPUState * env, target_ulong address,
+static int find_itlb_entry(CPUSH4State * env, target_ulong address,
int use_asid)
{
int e;
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
{
/* per utlb access */
increment_urc(env);
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
-static int get_mmu_address(CPUState * env, target_ulong * physical,
+static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
int rw, int access_type)
{
return n;
}
-static int get_physical_address(CPUState * env, target_ulong * physical,
+static int get_physical_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
int rw, int access_type)
{
return get_mmu_address(env, physical, prot, address, rw, access_type);
}
-int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
target_ulong physical;
int prot, ret, access_type;
switch (ret) {
case MMU_ITLB_MISS:
case MMU_DTLB_MISS_READ:
- env->exception_index = 0x040;
+ cs->exception_index = 0x040;
break;
case MMU_DTLB_MULTIPLE:
case MMU_ITLB_MULTIPLE:
- env->exception_index = 0x140;
+ cs->exception_index = 0x140;
break;
case MMU_ITLB_VIOLATION:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
case MMU_DTLB_MISS_WRITE:
- env->exception_index = 0x060;
+ cs->exception_index = 0x060;
break;
case MMU_DTLB_INITIAL_WRITE:
- env->exception_index = 0x080;
+ cs->exception_index = 0x080;
break;
case MMU_DTLB_VIOLATION_READ:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
case MMU_DTLB_VIOLATION_WRITE:
- env->exception_index = 0x0c0;
+ cs->exception_index = 0x0c0;
break;
case MMU_IADDR_ERROR:
case MMU_DADDR_ERROR_READ:
- env->exception_index = 0x0e0;
+ cs->exception_index = 0x0e0;
break;
case MMU_DADDR_ERROR_WRITE:
- env->exception_index = 0x100;
+ cs->exception_index = 0x100;
break;
default:
- cpu_abort(env, "Unhandled MMU fault");
+ cpu_abort(cs, "Unhandled MMU fault");
}
return 1;
}
address &= TARGET_PAGE_MASK;
physical &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
target_ulong physical;
int prot;
- get_physical_address(env, &physical, &prot, addr, 0, 0);
+ get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
return physical;
}
void cpu_load_tlb(CPUSH4State * env)
{
+ SuperHCPU *cpu = sh_env_get_cpu(env);
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(env, address);
+ tlb_flush_page(CPU(cpu), address);
}
/* Take values into cpu status from registers. */
entry->size = 1024 * 1024; /* 1M */
break;
default:
- cpu_abort(env, "Unhandled load_tlb");
+ cpu_abort(CPU(cpu), "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
entry->v = 0;
}
- tlb_flush(s, 1);
+ tlb_flush(CPU(sh_env_get_cpu(s)), 1);
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int index = (addr & 0x00000300) >> 8;
tlb_t * entry = &s->itlb[index];
(entry->asid);
}
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
}
entry->asid = asid;
entry->vpn = vpn;
}
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00000300) >> 8;
}
}
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
}
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
(entry->asid);
}
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
int associate = addr & 0x0000080;
if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) {
+ CPUState *cs = CPU(sh_env_get_cpu(s));
+
/* Multiple TLB Exception */
- s->exception_index = 0x140;
+ cs->exception_index = 0x140;
s->tea = addr;
break;
}
}
}
- if (needs_tlb_flush)
- tlb_flush_page(s, vpn << 10);
+ if (needs_tlb_flush) {
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
+ }
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
if (entry->v) {
+ CPUState *cs = CPU(sh_env_get_cpu(s));
+
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(cs, address);
}
entry->asid = asid;
entry->vpn = vpn;
}
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00003f00) >> 8;
}
}
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
/*
* TODO : Evaluate CCR and check if the cache is on or off.
* Now CCR is not in CPUSH4State, but in SH7750State.
- * When you move the ccr inot CPUSH4State, the code will be
+ * When you move the ccr into CPUSH4State, the code will be
* as follows.
*/
#if 0
}
#endif
+
+bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ superh_cpu_do_interrupt(cs);
+ return true;
+ }
+ return false;
+}
projects / qemu.git / blobdiff