* THE SOFTWARE.
*/
-#include "hw.h"
-#include "sun4m.h"
-#include "monitor.h"
-#include "sysbus.h"
+#include "hw/hw.h"
+#include "hw/sun4m.h"
+#include "monitor/monitor.h"
+#include "hw/sysbus.h"
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ
typedef struct Sun4c_INTCTLState {
SysBusDevice busdev;
+ MemoryRegion iomem;
#ifdef DEBUG_IRQ_COUNT
uint64_t irq_count;
#endif
static void sun4c_check_interrupts(void *opaque);
-static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
+ unsigned size)
{
Sun4c_INTCTLState *s = opaque;
uint32_t ret;
return ret;
}
-static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
{
Sun4c_INTCTLState *s = opaque;
- DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
+ DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val);
val &= 0xbf;
s->reg = val;
sun4c_check_interrupts(s);
}
-static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
- sun4c_intctl_mem_readb,
- NULL,
- NULL,
+static const MemoryRegionOps sun4c_intctl_mem_ops = {
+ .read = sun4c_intctl_mem_read,
+ .write = sun4c_intctl_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
-static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
- sun4c_intctl_mem_writeb,
- NULL,
- NULL,
-};
-
-void sun4c_pic_info(Monitor *mon, void *opaque)
-{
- Sun4c_INTCTLState *s = opaque;
-
- monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
- s->pending, s->reg);
-}
-
-void sun4c_irq_info(Monitor *mon, void *opaque)
-{
-#ifndef DEBUG_IRQ_COUNT
- monitor_printf(mon, "irq statistic code not compiled.\n");
-#else
- Sun4c_INTCTLState *s = opaque;
- int64_t count;
-
- monitor_printf(mon, "IRQ statistics:\n");
- count = s->irq_count;
- if (count > 0)
- monitor_printf(mon, " %" PRId64 "\n", count);
-#endif
-}
-
static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
static void sun4c_check_interrupts(void *opaque)
}
}
-static void sun4c_intctl_save(QEMUFile *f, void *opaque)
-{
- Sun4c_INTCTLState *s = opaque;
-
- qemu_put_8s(f, &s->reg);
- qemu_put_8s(f, &s->pending);
-}
-
-static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
-{
- Sun4c_INTCTLState *s = opaque;
-
- if (version_id != 1)
- return -EINVAL;
-
- qemu_get_8s(f, &s->reg);
- qemu_get_8s(f, &s->pending);
-
- return 0;
-}
+static const VMStateDescription vmstate_sun4c_intctl = {
+ .name ="sun4c_intctl",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(reg, Sun4c_INTCTLState),
+ VMSTATE_UINT8(pending, Sun4c_INTCTLState),
+ VMSTATE_END_OF_LIST()
+ }
+};
-static void sun4c_intctl_reset(void *opaque)
+static void sun4c_intctl_reset(DeviceState *d)
{
- Sun4c_INTCTLState *s = opaque;
+ Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
s->reg = 1;
s->pending = 0;
}
-DeviceState *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq *parent_irq)
+static int sun4c_intctl_init1(SysBusDevice *dev)
{
- DeviceState *dev;
- SysBusDevice *s;
+ Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
unsigned int i;
- dev = qdev_create(NULL, "sun4c_intctl");
- qdev_init(dev);
-
- s = sysbus_from_qdev(dev);
+ memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,
+ "intctl", INTCTL_SIZE);
+ sysbus_init_mmio(dev, &s->iomem);
+ qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
for (i = 0; i < MAX_PILS; i++) {
- sysbus_connect_irq(s, i, parent_irq[i]);
+ sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
- sysbus_mmio_map(s, 0, addr);
- return dev;
+ return 0;
}
-static void sun4c_intctl_init1(SysBusDevice *dev)
+static void sun4c_intctl_class_init(ObjectClass *klass, void *data)
{
- Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
- int io_memory;
- unsigned int i;
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
- sun4c_intctl_mem_write, s);
- sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
- qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
-
- for (i = 0; i < MAX_PILS; i++) {
- sysbus_init_irq(dev, &s->cpu_irqs[i]);
- }
- register_savevm("sun4c_intctl", -1, 1, sun4c_intctl_save,
- sun4c_intctl_load, s);
- qemu_register_reset(sun4c_intctl_reset, s);
- sun4c_intctl_reset(s);
+ k->init = sun4c_intctl_init1;
+ dc->reset = sun4c_intctl_reset;
+ dc->vmsd = &vmstate_sun4c_intctl;
}
-static SysBusDeviceInfo sun4c_intctl_info = {
- .init = sun4c_intctl_init1,
- .qdev.name = "sun4c_intctl",
- .qdev.size = sizeof(Sun4c_INTCTLState),
+static const TypeInfo sun4c_intctl_info = {
+ .name = "sun4c_intctl",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Sun4c_INTCTLState),
+ .class_init = sun4c_intctl_class_init,
};
-static void sun4c_intctl_register_devices(void)
+static void sun4c_intctl_register_types(void)
{
- sysbus_register_withprop(&sun4c_intctl_info);
+ type_register_static(&sun4c_intctl_info);
}
-device_init(sun4c_intctl_register_devices)
+type_init(sun4c_intctl_register_types)
projects / qemu.git / blobdiff