/*
- * QEMU Floppy disk emulator
+ * QEMU Floppy disk emulator (Intel 82078)
*
- * Copyright (c) 2003 Jocelyn Mayer
+ * Copyright (c) 2003, 2007 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+/*
+ * The controller is used in Sun4m systems in a slightly different
+ * way. There are changes in DOR register and DMA is not available.
+ */
#include "vl.h"
/********************************************************/
typedef enum fdrive_flags_t {
FDRIVE_MOTOR_ON = 0x01, /* motor on/off */
- FDRIVE_REVALIDATE = 0x02, /* Revalidated */
} fdrive_flags_t;
typedef enum fdisk_flags_t {
{
/* Drive */
drv->bs = bs;
- if (bs)
- drv->drive = FDRIVE_DRV_144;
- else
- drv->drive = FDRIVE_DRV_NONE;
+ drv->drive = FDRIVE_DRV_NONE;
drv->drflags = 0;
drv->perpendicular = 0;
/* Disk */
int nb_heads, max_track, last_sect, ro;
FLOPPY_DPRINTF("revalidate\n");
- drv->drflags &= ~FDRIVE_REVALIDATE;
if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
ro = bdrv_is_read_only(drv->bs);
bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
drv->max_track = 0;
drv->flags &= ~FDISK_DBL_SIDES;
}
- drv->drflags |= FDRIVE_REVALIDATE;
}
/* Motor control */
}
/********************************************************/
-/* Intel 82078 floppy disk controler emulation */
+/* Intel 82078 floppy disk controller emulation */
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
-static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size);
+static int fdctrl_transfer_handler (void *opaque, int nchan,
+ int dma_pos, int dma_len);
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status);
static void fdctrl_result_timer(void *opaque);
struct fdctrl_t {
fdctrl_t *fdctrl;
- /* Controler's identification */
+ /* Controller's identification */
uint8_t version;
/* HW */
- int irq_lvl;
+ qemu_irq irq;
int dma_chann;
- uint32_t io_base;
- /* Controler state */
+ target_phys_addr_t io_base;
+ /* Controller state */
QEMUTimer *result_timer;
uint8_t state;
uint8_t dma_en;
uint8_t data_state;
uint8_t data_dir;
uint8_t int_status;
+ uint8_t eot; /* last wanted sector */
/* States kept only to be returned back */
/* Timers state */
uint8_t timer0;
uint32_t retval;
switch (reg & 0x07) {
+#ifdef TARGET_SPARC
+ case 0x00:
+ // Identify to Linux as S82078B
+ retval = fdctrl_read_statusB(fdctrl);
+ break;
+#endif
case 0x01:
retval = fdctrl_read_statusB(fdctrl);
break;
}
}
-static void fd_change_cb (void *opaque)
+static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
- fdrive_t *drv = opaque;
+ return fdctrl_read(opaque, (uint32_t)reg);
+}
- FLOPPY_DPRINTF("disk change\n");
- fd_revalidate(drv);
-#if 0
- fd_recalibrate(drv);
- fdctrl_reset_fifo(drv->fdctrl);
- fdctrl_raise_irq(drv->fdctrl, 0x20);
-#endif
+static void fdctrl_write_mem (void *opaque,
+ target_phys_addr_t reg, uint32_t value)
+{
+ fdctrl_write(opaque, (uint32_t)reg, value);
+}
+
+static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
+ fdctrl_read_mem,
+ fdctrl_read_mem,
+ fdctrl_read_mem,
+};
+
+static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
+ fdctrl_write_mem,
+ fdctrl_write_mem,
+ fdctrl_write_mem,
+};
+
+static void fd_save (QEMUFile *f, fdrive_t *fd)
+{
+ uint8_t tmp;
+
+ tmp = fd->drflags;
+ qemu_put_8s(f, &tmp);
+ qemu_put_8s(f, &fd->head);
+ qemu_put_8s(f, &fd->track);
+ qemu_put_8s(f, &fd->sect);
+ qemu_put_8s(f, &fd->dir);
+ qemu_put_8s(f, &fd->rw);
+}
+
+static void fdc_save (QEMUFile *f, void *opaque)
+{
+ fdctrl_t *s = opaque;
+
+ qemu_put_8s(f, &s->state);
+ qemu_put_8s(f, &s->dma_en);
+ qemu_put_8s(f, &s->cur_drv);
+ qemu_put_8s(f, &s->bootsel);
+ qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
+ qemu_put_be32s(f, &s->data_pos);
+ qemu_put_be32s(f, &s->data_len);
+ qemu_put_8s(f, &s->data_state);
+ qemu_put_8s(f, &s->data_dir);
+ qemu_put_8s(f, &s->int_status);
+ qemu_put_8s(f, &s->eot);
+ qemu_put_8s(f, &s->timer0);
+ qemu_put_8s(f, &s->timer1);
+ qemu_put_8s(f, &s->precomp_trk);
+ qemu_put_8s(f, &s->config);
+ qemu_put_8s(f, &s->lock);
+ qemu_put_8s(f, &s->pwrd);
+ fd_save(f, &s->drives[0]);
+ fd_save(f, &s->drives[1]);
+}
+
+static int fd_load (QEMUFile *f, fdrive_t *fd)
+{
+ uint8_t tmp;
+
+ qemu_get_8s(f, &tmp);
+ fd->drflags = tmp;
+ qemu_get_8s(f, &fd->head);
+ qemu_get_8s(f, &fd->track);
+ qemu_get_8s(f, &fd->sect);
+ qemu_get_8s(f, &fd->dir);
+ qemu_get_8s(f, &fd->rw);
+
+ return 0;
+}
+
+static int fdc_load (QEMUFile *f, void *opaque, int version_id)
+{
+ fdctrl_t *s = opaque;
+ int ret;
+
+ if (version_id != 1)
+ return -EINVAL;
+
+ qemu_get_8s(f, &s->state);
+ qemu_get_8s(f, &s->dma_en);
+ qemu_get_8s(f, &s->cur_drv);
+ qemu_get_8s(f, &s->bootsel);
+ qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
+ qemu_get_be32s(f, &s->data_pos);
+ qemu_get_be32s(f, &s->data_len);
+ qemu_get_8s(f, &s->data_state);
+ qemu_get_8s(f, &s->data_dir);
+ qemu_get_8s(f, &s->int_status);
+ qemu_get_8s(f, &s->eot);
+ qemu_get_8s(f, &s->timer0);
+ qemu_get_8s(f, &s->timer1);
+ qemu_get_8s(f, &s->precomp_trk);
+ qemu_get_8s(f, &s->config);
+ qemu_get_8s(f, &s->lock);
+ qemu_get_8s(f, &s->pwrd);
+
+ ret = fd_load(f, &s->drives[0]);
+ if (ret == 0)
+ ret = fd_load(f, &s->drives[1]);
+
+ return ret;
}
-fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
- uint32_t io_base,
+static void fdctrl_external_reset(void *opaque)
+{
+ fdctrl_t *s = opaque;
+
+ fdctrl_reset(s, 0);
+}
+
+fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
+ target_phys_addr_t io_base,
BlockDriverState **fds)
{
fdctrl_t *fdctrl;
-// int io_mem;
+ int io_mem;
int i;
- FLOPPY_DPRINTF("init controler\n");
+ FLOPPY_DPRINTF("init controller\n");
fdctrl = qemu_mallocz(sizeof(fdctrl_t));
if (!fdctrl)
return NULL;
fdctrl->result_timer = qemu_new_timer(vm_clock,
fdctrl_result_timer, fdctrl);
- fdctrl->version = 0x90; /* Intel 82078 controler */
- fdctrl->irq_lvl = irq_lvl;
+ fdctrl->version = 0x90; /* Intel 82078 controller */
+ fdctrl->irq = irq;
fdctrl->dma_chann = dma_chann;
fdctrl->io_base = io_base;
fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */
}
for (i = 0; i < 2; i++) {
fd_init(&fdctrl->drives[i], fds[i]);
- if (fds[i]) {
- bdrv_set_change_cb(fds[i],
- &fd_change_cb, &fdctrl->drives[i]);
- }
}
fdctrl_reset(fdctrl, 0);
fdctrl->state = FD_CTRL_ACTIVE;
if (mem_mapped) {
- FLOPPY_ERROR("memory mapped floppy not supported by now !\n");
-#if 0
- io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write);
- cpu_register_physical_memory(base, 0x08, io_mem);
-#endif
+ io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl);
+ cpu_register_physical_memory(io_base, 0x08, io_mem);
} else {
- register_ioport_read(io_base + 0x01, 5, 1, &fdctrl_read, fdctrl);
- register_ioport_read(io_base + 0x07, 1, 1, &fdctrl_read, fdctrl);
- register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl);
- register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl);
+ register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
+ fdctrl);
+ register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
+ fdctrl);
+ register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
+ fdctrl);
+ register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
+ fdctrl);
}
+ register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
+ qemu_register_reset(fdctrl_external_reset, fdctrl);
for (i = 0; i < 2; i++) {
fd_revalidate(&fdctrl->drives[i]);
}
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
{
FLOPPY_DPRINTF("Reset interrupt\n");
- pic_set_irq(fdctrl->irq_lvl, 0);
+ qemu_set_irq(fdctrl->irq, 0);
fdctrl->state &= ~FD_CTRL_INTR;
}
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
{
+#ifdef TARGET_SPARC
+ // Sparc mutation
+ if (!fdctrl->dma_en) {
+ fdctrl->state &= ~FD_CTRL_BUSY;
+ fdctrl->int_status = status;
+ return;
+ }
+#endif
if (~(fdctrl->state & FD_CTRL_INTR)) {
- pic_set_irq(fdctrl->irq_lvl, 1);
+ qemu_set_irq(fdctrl->irq, 1);
fdctrl->state |= FD_CTRL_INTR;
}
FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
fdctrl->int_status = status;
}
-/* Reset controler */
+/* Reset controller */
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
{
int i;
- FLOPPY_DPRINTF("reset controler\n");
+ FLOPPY_DPRINTF("reset controller\n");
fdctrl_reset_irq(fdctrl);
- /* Initialise controler */
+ /* Initialise controller */
fdctrl->cur_drv = 0;
/* FIFO state */
fdctrl->data_pos = 0;
/* Reset mode */
if (fdctrl->state & FD_CTRL_RESET) {
if (!(value & 0x04)) {
- FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
+ FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
}
/* Reset */
if (!(value & 0x04)) {
if (!(fdctrl->state & FD_CTRL_RESET)) {
- FLOPPY_DPRINTF("controler enter RESET state\n");
+ FLOPPY_DPRINTF("controller enter RESET state\n");
fdctrl->state |= FD_CTRL_RESET;
}
} else {
if (fdctrl->state & FD_CTRL_RESET) {
- FLOPPY_DPRINTF("controler out of RESET state\n");
+ FLOPPY_DPRINTF("controller out of RESET state\n");
fdctrl_reset(fdctrl, 1);
fdctrl->state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP);
}
{
/* Reset mode */
if (fdctrl->state & FD_CTRL_RESET) {
- FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
+ FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
{
/* Reset mode */
if (fdctrl->state & FD_CTRL_RESET) {
- FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
+ FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
// fdctrl.precomp = (value >> 2) & 0x07;
}
+static int fdctrl_media_changed(fdrive_t *drv)
+{
+ int ret;
+ if (!drv->bs)
+ return 0;
+ ret = bdrv_media_changed(drv->bs);
+ if (ret) {
+ fd_revalidate(drv);
+ }
+ return ret;
+}
+
/* Digital input register : 0x07 (read-only) */
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
{
uint32_t retval = 0;
- if (drv0(fdctrl)->drflags & FDRIVE_REVALIDATE ||
- drv1(fdctrl)->drflags & FDRIVE_REVALIDATE)
+ if (fdctrl_media_changed(drv0(fdctrl)) ||
+ fdctrl_media_changed(drv1(fdctrl)))
retval |= 0x80;
if (retval != 0)
FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
- drv0(fdctrl)->drflags &= ~FDRIVE_REVALIDATE;
- drv1(fdctrl)->drflags &= ~FDRIVE_REVALIDATE;
return retval;
}
fdrive_t *cur_drv;
cur_drv = get_cur_drv(fdctrl);
- fdctrl->fifo[0] = 0x60 | (cur_drv->head << 1) | fdctrl->cur_drv;
+ fdctrl->fifo[0] = 0x60 | (cur_drv->head << 2) | fdctrl->cur_drv;
fdctrl->fifo[1] = 0x00;
fdctrl->fifo[2] = 0x00;
fdctrl_set_fifo(fdctrl, 3, 1);
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
status0, status1, status2,
- status0 | (cur_drv->head << 1) | fdctrl->cur_drv);
- fdctrl->fifo[0] = status0 | (cur_drv->head << 1) | fdctrl->cur_drv;
+ status0 | (cur_drv->head << 2) | fdctrl->cur_drv);
+ fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
fdctrl->fifo[1] = status1;
fdctrl->fifo[2] = status2;
fdctrl->fifo[3] = cur_drv->track;
kt = fdctrl->fifo[2];
kh = fdctrl->fifo[3];
ks = fdctrl->fifo[4];
- FLOPPY_DPRINTF("Start tranfert at %d %d %02x %02x (%d)\n",
+ FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
fdctrl->cur_drv, kh, kt, ks,
_fd_sector(kh, kt, ks, cur_drv->last_sect));
did_seek = 0;
fdctrl->data_len = fdctrl->fifo[8];
} else {
int tmp;
- fdctrl->data_len = 128 << fdctrl->fifo[5];
+ fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
tmp = (cur_drv->last_sect - ks + 1);
if (fdctrl->fifo[0] & 0x80)
tmp += cur_drv->last_sect;
fdctrl->data_len *= tmp;
}
+ fdctrl->eot = fdctrl->fifo[6];
if (fdctrl->dma_en) {
int dma_mode;
/* DMA transfer are enabled. Check if DMA channel is well programmed */
(direction == FD_DIR_READ && dma_mode == 1)) {
/* No access is allowed until DMA transfer has completed */
fdctrl->state |= FD_CTRL_BUSY;
- /* Now, we just have to wait for the DMA controler to
+ /* Now, we just have to wait for the DMA controller to
* recall us...
*/
DMA_hold_DREQ(fdctrl->dma_chann);
}
/* handlers for DMA transfers */
-static int fdctrl_transfer_handler (void *opaque, target_ulong addr, int size)
+static int fdctrl_transfer_handler (void *opaque, int nchan,
+ int dma_pos, int dma_len)
{
fdctrl_t *fdctrl;
fdrive_t *cur_drv;
if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
fdctrl->data_dir == FD_DIR_SCANH)
status2 = 0x04;
- if (size > fdctrl->data_len)
- size = fdctrl->data_len;
- if (cur_drv->bs == NULL) {
+ if (dma_len > fdctrl->data_len)
+ dma_len = fdctrl->data_len;
+ if (cur_drv->bs == NULL) {
if (fdctrl->data_dir == FD_DIR_WRITE)
fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
else
fdctrl_stop_transfer(fdctrl, 0x40, 0x00, 0x00);
len = 0;
- goto transfer_error;
- }
+ goto transfer_error;
+ }
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
- for (start_pos = fdctrl->data_pos; fdctrl->data_pos < size;) {
- len = size - fdctrl->data_pos;
+ for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
+ len = dma_len - fdctrl->data_pos;
if (len + rel_pos > FD_SECTOR_LEN)
len = FD_SECTOR_LEN - rel_pos;
- FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x %02x "
- "(%d-0x%08x 0x%08x)\n", len, size, fdctrl->data_pos,
+ FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
+ "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
fdctrl->data_len, fdctrl->cur_drv, cur_drv->head,
cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
- fd_sector(cur_drv) * 512, addr);
+ fd_sector(cur_drv) * 512);
if (fdctrl->data_dir != FD_DIR_WRITE ||
len < FD_SECTOR_LEN || rel_pos != 0) {
/* READ & SCAN commands and realign to a sector for WRITE */
/* Sure, image size is too small... */
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
}
- }
+ }
switch (fdctrl->data_dir) {
case FD_DIR_READ:
/* READ commands */
- cpu_physical_memory_write(addr + fdctrl->data_pos,
- fdctrl->fifo + rel_pos, len);
+ DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
+ fdctrl->data_pos, len);
+/* cpu_physical_memory_write(addr + fdctrl->data_pos, */
+/* fdctrl->fifo + rel_pos, len); */
break;
case FD_DIR_WRITE:
/* WRITE commands */
- cpu_physical_memory_read(addr + fdctrl->data_pos,
- fdctrl->fifo + rel_pos, len);
+ DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
+ fdctrl->data_pos, len);
+/* cpu_physical_memory_read(addr + fdctrl->data_pos, */
+/* fdctrl->fifo + rel_pos, len); */
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
fdctrl->fifo, 1) < 0) {
FLOPPY_ERROR("writting sector %d\n", fd_sector(cur_drv));
fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
goto transfer_error;
- }
+ }
break;
default:
/* SCAN commands */
{
uint8_t tmpbuf[FD_SECTOR_LEN];
int ret;
- cpu_physical_memory_read(addr + fdctrl->data_pos,
- tmpbuf, len);
+ DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
+/* cpu_physical_memory_read(addr + fdctrl->data_pos, */
+/* tmpbuf, len); */
ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
if (ret == 0) {
status2 = 0x08;
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
if (rel_pos == 0) {
/* Seek to next sector */
- cur_drv->sect++;
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d) (%d)\n",
cur_drv->head, cur_drv->track, cur_drv->sect,
fd_sector(cur_drv),
- fdctrl->data_pos - size);
- if (cur_drv->sect > cur_drv->last_sect) {
+ fdctrl->data_pos - len);
+ /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
+ error in fact */
+ if (cur_drv->sect >= cur_drv->last_sect ||
+ cur_drv->sect == fdctrl->eot) {
cur_drv->sect = 1;
if (FD_MULTI_TRACK(fdctrl->data_state)) {
if (cur_drv->head == 0 &&
(cur_drv->flags & FDISK_DBL_SIDES) != 0) {
- cur_drv->head = 1;
- } else {
- cur_drv->head = 0;
+ cur_drv->head = 1;
+ } else {
+ cur_drv->head = 0;
cur_drv->track++;
if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
break;
+ }
+ } else {
+ cur_drv->track++;
+ break;
}
- } else {
- cur_drv->track++;
- break;
- }
FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
cur_drv->head, cur_drv->track,
cur_drv->sect, fd_sector(cur_drv));
+ } else {
+ cur_drv->sect++;
}
}
}
status0 |= 0x20;
fdctrl->data_len -= len;
// if (fdctrl->data_len == 0)
- fdctrl_stop_transfer(fdctrl, status0, status1, status2);
+ fdctrl_stop_transfer(fdctrl, status0, status1, status2);
transfer_error:
return len;
retval = fdctrl->fifo[pos];
if (++fdctrl->data_pos == fdctrl->data_len) {
fdctrl->data_pos = 0;
- /* Switch from transfert mode to status mode
+ /* Switch from transfer mode to status mode
* then from status mode to command mode
*/
if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
cur_drv = get_cur_drv(fdctrl);
/* Reset mode */
if (fdctrl->state & FD_CTRL_RESET) {
- FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
+ FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
fdctrl->state &= ~FD_CTRL_SLEEP;
bdrv_write(cur_drv->bs, fd_sector(cur_drv),
fdctrl->fifo, FD_SECTOR_LEN);
}
- /* Switch from transfert mode to status mode
+ /* Switch from transfer mode to status mode
* then from status mode to command mode
*/
if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA)
FLOPPY_DPRINTF("SENSE_INTERRUPT_STATUS command (%02x)\n",
fdctrl->int_status);
/* No parameters cmd: returns status if no interrupt */
+#if 0
fdctrl->fifo[0] =
fdctrl->int_status | (cur_drv->head << 2) | fdctrl->cur_drv;
+#else
+ /* XXX: int_status handling is broken for read/write
+ commands, so we do this hack. It should be suppressed
+ ASAP */
+ fdctrl->fifo[0] =
+ 0x20 | (cur_drv->head << 2) | fdctrl->cur_drv;
+#endif
fdctrl->fifo[1] = cur_drv->track;
fdctrl_set_fifo(fdctrl, 2, 0);
fdctrl_reset_irq(fdctrl);
/* VERSION */
FLOPPY_DPRINTF("VERSION command\n");
/* No parameters cmd */
- /* Controler's version */
+ /* Controller's version */
fdctrl->fifo[0] = fdctrl->version;
fdctrl_set_fifo(fdctrl, 1, 1);
return;
/* 1 Byte status back */
fdctrl->fifo[0] = (cur_drv->ro << 6) |
(cur_drv->track == 0 ? 0x10 : 0x00) |
- fdctrl->cur_drv;
+ (cur_drv->head << 2) |
+ fdctrl->cur_drv |
+ 0x28;
fdctrl_set_fifo(fdctrl, 1, 0);
break;
case 0x07:
/* READ_ID */
FLOPPY_DPRINTF("treat READ_ID command\n");
/* XXX: should set main status register to busy */
+ cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
qemu_mod_timer(fdctrl->result_timer,
qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
break;
#else
cur_drv->last_sect = fdctrl->fifo[3];
#endif
- /* Bochs BIOS is buggy and don't send format informations
- * for each sector. So, pretend all's done right now...
+ /* TODO: implement format using DMA expected by the Bochs BIOS
+ * and Linux fdformat (read 3 bytes per sector via DMA and fill
+ * the sector with the specified fill byte
*/
fdctrl->data_state &= ~FD_STATE_FORMAT;
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
projects / qemu.git / blobdiff