MIPS TLB style selection at runtime, by Herve Poussineau.

[qemu.git] / mips-dis.c

diff --git a/mips-dis.c b/mips-dis.c
index fbc64c77ced7c51ac2c5de8170a36819f0c80f9d..2e7dc85d1d8275764b97268b91fa9d986710c84d 100644 (file)
--- a/mips-dis.c
+++ b/mips-dis.c
@@ -528,6 +528,7 @@ struct mips_opcode
    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
    test, or zero if no CPU specific ISA test is desired.  */
 
+#if 0
 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
     (((insn)->membership & isa) != 0                                   \
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
@@ -543,6 +544,10 @@ struct mips_opcode
      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)   \
      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)   \
      || 0)     /* Please keep this term for easier source merging.  */
+#else
+#define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
+    (1 != 0)
+#endif
 
 /* This is a list of macro expanded instructions.
 
@@ -2155,10 +2160,6 @@ struct mips_opcode *mips_opcodes =
 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
 #undef MIPS_NUM_OPCODES
 
-typedef int bfd_boolean;
-#define TRUE (1)
-#define FALSE (0)
-
 /* Mips instructions are at maximum this many bytes long.  */
 #define INSNLEN 4