#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu-common.h"
#include "hw/arm/fsl-imx6.h"
+#include "hw/usb/imx-usb-phy.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
#include "sysemu/sysemu.h"
#include "chardev/char.h"
#include "qemu/error-report.h"
+#include "qemu/module.h"
+
+#define IMX6_ESDHC_CAPABILITIES 0x057834b4
#define NAME_SIZE 20
static void fsl_imx6_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(obj);
char name[NAME_SIZE];
int i;
- if (smp_cpus > FSL_IMX6_NUM_CPUS) {
- error_report("%s: Only %d CPUs are supported (%d requested)",
- TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
- exit(1);
- }
-
- for (i = 0; i < smp_cpus; i++) {
- object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
- "cortex-a9-" TYPE_ARM_CPU);
+ for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
- object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL);
+ object_initialize_child(obj, name, &s->cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-a9"));
}
- object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV);
- qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default());
- object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL);
+ object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
- object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
- qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
- object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL);
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
- object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC);
- qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default());
- object_property_add_child(obj, "src", OBJECT(&s->src), NULL);
+ object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
- object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
- qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "uart%d", i + 1);
- object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
+ object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
- object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
- qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
- object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
+ object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
- object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
- qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "epit%d", i + 1);
- object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL);
+ object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
}
for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
- object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
- qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
- object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL);
+ object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
}
for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
- object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
- qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "gpio%d", i + 1);
- object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL);
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
}
for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
- object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC);
- qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
- object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL);
+ object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
+ }
+
+ for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+ snprintf(name, NAME_SIZE, "usbphy%d", i);
+ object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
+ }
+ for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+ snprintf(name, NAME_SIZE, "usb%d", i);
+ object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
}
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
- object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI);
- qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
snprintf(name, NAME_SIZE, "spi%d", i + 1);
- object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL);
+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
+ }
+ for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
+ snprintf(name, NAME_SIZE, "wdt%d", i);
+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
}
- object_initialize(&s->eth, sizeof(s->eth), TYPE_IMX_ENET);
- qdev_set_parent_bus(DEVICE(&s->eth), sysbus_get_default());
- object_property_add_child(obj, "eth", OBJECT(&s->eth), NULL);
+
+ object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(dev);
uint16_t i;
Error *err = NULL;
+ unsigned int smp_cpus = ms->smp.cpus;
+
+ if (smp_cpus > FSL_IMX6_NUM_CPUS) {
+ error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
+ TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
+ return;
+ }
for (i = 0; i < smp_cpus; i++) {
/* On uniprocessor, the CBAR is set to 0 */
if (smp_cpus > 1) {
- object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
- "reset-cbar", &error_abort);
+ object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+ FSL_IMX6_A9MPCORE_ADDR, &error_abort);
}
/* All CPU but CPU 0 start in power off mode */
if (i) {
- object_property_set_bool(OBJECT(&s->cpu[i]), true,
- "start-powered-off", &error_abort);
+ object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
+ true, &error_abort);
}
- object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return;
}
}
- object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
+ object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->a9mpcore),
- FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
- &error_abort);
+ object_property_set_int(OBJECT(&s->a9mpcore), "num-irq",
+ FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
- object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
- object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
- object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
{ FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
};
- if (i < MAX_SERIAL_PORTS) {
- Chardev *chr;
-
- chr = serial_hds[i];
-
- if (!chr) {
- char *label = g_strdup_printf("imx6.uart%d", i + 1);
- chr = qemu_chr_new(label, "null");
- g_free(label);
- serial_hds[i] = chr;
- }
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
- qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
- }
-
- object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
return;
}
s->gpt.ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
return;
}
s->epit[i].ccm = IMX_CCM(&s->ccm);
- object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) {
return;
}
{ FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
};
- object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
return;
}
},
};
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
- &error_abort);
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
+ object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
&error_abort);
- object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
+ true, &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
return;
}
{ FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
};
- object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
+ object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3,
+ &error_abort);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg",
+ IMX6_ESDHC_CAPABILITIES, &error_abort);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor",
+ SDHCI_VENDOR_IMX, &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
esdhc_table[i].irq));
}
+ /* USB */
+ for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+ sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+ FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
+ }
+ for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+ static const int FSL_IMX6_USBn_IRQ[] = {
+ FSL_IMX6_USB_OTG_IRQ,
+ FSL_IMX6_USB_HOST1_IRQ,
+ FSL_IMX6_USB_HOST2_IRQ,
+ FSL_IMX6_USB_HOST3_IRQ,
+ };
+
+ sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
+ FSL_IMX6_USBn_IRQ[i]));
+ }
+
/* Initialize all ECSPI */
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
static const struct {
};
/* Initialize the SPI */
- object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
return;
}
spi_table[i].irq));
}
+ object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
- object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
FSL_IMX6_ENET_MAC_1588_IRQ));
+ /*
+ * Watchdog
+ */
+ for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
+ static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
+ FSL_IMX6_WDOG1_ADDR,
+ FSL_IMX6_WDOG2_ADDR,
+ };
+ static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
+ FSL_IMX6_WDOG1_IRQ,
+ FSL_IMX6_WDOG2_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
+ true, &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
+ FSL_IMX6_WDOGn_IRQ[i]));
+ }
+
/* ROM memory */
- memory_region_init_rom(&s->rom, NULL, "imx6.rom",
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
FSL_IMX6_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
&s->rom);
/* CAAM memory */
- memory_region_init_rom(&s->caam, NULL, "imx6.caam",
+ memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
FSL_IMX6_CAAM_MEM_SIZE, &err);
if (err) {
error_propagate(errp, err);
&s->ocram);
/* internal OCRAM (256 KB) is aliased over 1 MB */
- memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
+ memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
&s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
&s->ocram_alias);
}
+static Property fsl_imx6_properties[] = {
+ DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void fsl_imx6_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, fsl_imx6_properties);
dc->realize = fsl_imx6_realize;
dc->desc = "i.MX6 SOC";
- /* Reason: Uses serial_hds[] in the realize() function */
+ /* Reason: Uses serial_hd() in the realize() function */
dc->user_creatable = false;
}
projects / qemu.git / blobdiff