scsi-disk: fix DPRINTF

[qemu.git] / hw / prep_pci.c

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 39c812d51cf2928c25154e0c754475bc846ed934..58619ddf746204e22a739df2398c6dc7849dbc0c 100644 (file)
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -24,24 +24,11 @@
 
 #include "hw.h"
 #include "pci.h"
-
-typedef uint32_t pci_addr_t;
 #include "pci_host.h"
+#include "prep_pci.h"
 
 typedef PCIHostState PREPPCIState;
 
-static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
-{
-    PREPPCIState *s = opaque;
-    s->config_reg = val;
-}
-
-static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
-{
-    PREPPCIState *s = opaque;
-    return s->config_reg;
-}
-
 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
 {
     int i;
@@ -62,18 +49,14 @@ static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t va
 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     PREPPCIState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
     val = bswap16(val);
-#endif
     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
 }
 
 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     PREPPCIState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);
-#endif
     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
 }
 
@@ -90,9 +73,7 @@ static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
     PREPPCIState *s = opaque;
     uint32_t val;
     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
-#ifdef TARGET_WORDS_BIGENDIAN
     val = bswap16(val);
-#endif
     return val;
 }
 
@@ -101,19 +82,17 @@ static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
     PREPPCIState *s = opaque;
     uint32_t val;
     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
-#ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);
-#endif
     return val;
 }
 
-static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
+static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
     &PPC_PCIIO_writeb,
     &PPC_PCIIO_writew,
     &PPC_PCIIO_writel,
 };
 
-static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
+static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
     &PPC_PCIIO_readb,
     &PPC_PCIIO_readw,
     &PPC_PCIIO_readl,
@@ -124,32 +103,35 @@ static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 }
 
-static void prep_set_irq(qemu_irq *pic, int irq_num, int level)
+static void prep_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 }
 
-PCIBus *pci_prep_init(qemu_irq *pic)
+PCIBus *pci_prep_init(qemu_irq *pic,
+                      MemoryRegion *address_space_mem,
+                      MemoryRegion *address_space_io)
 {
     PREPPCIState *s;
     PCIDevice *d;
     int PPC_io_memory;
 
     s = qemu_mallocz(sizeof(PREPPCIState));
-    s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 4);
+    s->bus = pci_register_bus(NULL, "pci",
+                              prep_set_irq, prep_map_irq, pic,
+                              address_space_mem,
+                              address_space_io,
+                              0, 4);
 
-    register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
-    register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
+    pci_host_conf_register_ioport(0xcf8, s);
 
-    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
-    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
-    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
-    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
-    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
-    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
+    pci_host_data_register_ioport(0xcfc, s);
 
-    PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
-                                           PPC_PCIIO_write, s);
+    PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
+                                           PPC_PCIIO_write, s,
+                                           DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 
     /* PCI host bridge */
@@ -158,11 +140,9 @@ PCIBus *pci_prep_init(qemu_irq *pic)
     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
     d->config[0x08] = 0x00; // revision
-    d->config[0x0A] = 0x00; // class_sub = pci host
-    d->config[0x0B] = 0x06; // class_base = PCI_bridge
+    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
     d->config[0x0C] = 0x08; // cache_line_size
     d->config[0x0D] = 0x10; // latency_timer
-    d->config[0x0E] = 0x00; // header_type
     d->config[0x34] = 0x00; // capabilities_pointer
 
     return s->bus;