Add endianness as io mem parameter

[qemu.git] / hw / pxa2xx_pcmcia.c

diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index be1309f62e25dcef0651864e0c3e07e145c96715..50d4649f60db66baa817c288bd6ce8da85e7cea0 100644 (file)
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -140,19 +140,19 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
 
     /* Socket I/O Memory Space */
     iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
 
     /* Socket I/O Memory Space */
     iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,

-                    pxa2xx_pcmcia_io_writefn, s);
+                    pxa2xx_pcmcia_io_writefn, s, DEVICE_NATIVE_ENDIAN);

     cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
 
     /* Then next 64 MB is reserved */
 
     /* Socket Attribute Memory Space */
     iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
     cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
 
     /* Then next 64 MB is reserved */
 
     /* Socket Attribute Memory Space */
     iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,

-                    pxa2xx_pcmcia_attr_writefn, s);
+                    pxa2xx_pcmcia_attr_writefn, s, DEVICE_NATIVE_ENDIAN);

     cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
 
     /* Socket Common Memory Space */
     iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
     cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
 
     /* Socket Common Memory Space */
     iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,

-                    pxa2xx_pcmcia_common_writefn, s);
+                    pxa2xx_pcmcia_common_writefn, s, DEVICE_NATIVE_ENDIAN);

     cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
 
     if (base == 0x30000000)
     cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
 
     if (base == 0x30000000)