*/
#include "hw.h"
-#include "qemu-timer.h"
-#include "sysemu.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
#include "pxa.h"
#include "sysbus.h"
qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}
-static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
switch (offset) {
case OSMR3: tm ++;
+ /* fall through */
case OSMR2: tm ++;
+ /* fall through */
case OSMR1: tm ++;
+ /* fall through */
case OSMR0:
return s->timer[tm].value;
case OSMR11: tm ++;
+ /* fall through */
case OSMR10: tm ++;
+ /* fall through */
case OSMR9: tm ++;
+ /* fall through */
case OSMR8: tm ++;
+ /* fall through */
case OSMR7: tm ++;
+ /* fall through */
case OSMR6: tm ++;
+ /* fall through */
case OSMR5: tm ++;
+ /* fall through */
case OSMR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
s->lastload, s->freq, get_ticks_per_sec());
case OSCR11: tm ++;
+ /* fall through */
case OSCR10: tm ++;
+ /* fall through */
case OSCR9: tm ++;
+ /* fall through */
case OSCR8: tm ++;
+ /* fall through */
case OSCR7: tm ++;
+ /* fall through */
case OSCR6: tm ++;
+ /* fall through */
case OSCR5: tm ++;
+ /* fall through */
case OSCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
case OWER:
return s->reset3;
case OMCR11: tm ++;
+ /* fall through */
case OMCR10: tm ++;
+ /* fall through */
case OMCR9: tm ++;
+ /* fall through */
case OMCR8: tm ++;
+ /* fall through */
case OMCR7: tm ++;
+ /* fall through */
case OMCR6: tm ++;
+ /* fall through */
case OMCR5: tm ++;
+ /* fall through */
case OMCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
return 0;
}
-static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_timer_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i, tm = 0;
switch (offset) {
case OSMR3: tm ++;
+ /* fall through */
case OSMR2: tm ++;
+ /* fall through */
case OSMR1: tm ++;
+ /* fall through */
case OSMR0:
s->timer[tm].value = value;
pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
break;
case OSMR11: tm ++;
+ /* fall through */
case OSMR10: tm ++;
+ /* fall through */
case OSMR9: tm ++;
+ /* fall through */
case OSMR8: tm ++;
+ /* fall through */
case OSMR7: tm ++;
+ /* fall through */
case OSMR6: tm ++;
+ /* fall through */
case OSMR5: tm ++;
+ /* fall through */
case OSMR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
pxa2xx_timer_update(s, s->lastload);
break;
case OSCR11: tm ++;
+ /* fall through */
case OSCR10: tm ++;
+ /* fall through */
case OSCR9: tm ++;
+ /* fall through */
case OSCR8: tm ++;
+ /* fall through */
case OSCR7: tm ++;
+ /* fall through */
case OSCR6: tm ++;
+ /* fall through */
case OSCR5: tm ++;
+ /* fall through */
case OSCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->reset3 = value;
break;
case OMCR7: tm ++;
+ /* fall through */
case OMCR6: tm ++;
+ /* fall through */
case OMCR5: tm ++;
+ /* fall through */
case OMCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
}
break;
case OMCR11: tm ++;
+ /* fall through */
case OMCR10: tm ++;
+ /* fall through */
case OMCR9: tm ++;
+ /* fall through */
case OMCR8: tm += 4;
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
dc->props = pxa25x_timer_dev_properties;
}
-static TypeInfo pxa25x_timer_dev_info = {
+static const TypeInfo pxa25x_timer_dev_info = {
.name = "pxa25x-timer",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxTimerInfo),
dc->props = pxa27x_timer_dev_properties;
}
-static TypeInfo pxa27x_timer_dev_info = {
+static const TypeInfo pxa27x_timer_dev_info = {
.name = "pxa27x-timer",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxTimerInfo),
.class_init = pxa27x_timer_dev_class_init,
};
-static void pxa2xx_timer_register(void)
+static void pxa2xx_timer_register_types(void)
{
type_register_static(&pxa25x_timer_dev_info);
type_register_static(&pxa27x_timer_dev_info);
-};
-device_init(pxa2xx_timer_register);
+}
+
+type_init(pxa2xx_timer_register_types)