*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci.h"
+#include "migration/vmstate.h"
#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
#include "sysemu/block-backend.h"
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
static void ahci_unmap_clb_address(AHCIDevice *ad);
static void ahci_unmap_fis_address(AHCIDevice *ad);
+static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = {
+ [AHCI_HOST_REG_CAP] = "CAP",
+ [AHCI_HOST_REG_CTL] = "GHC",
+ [AHCI_HOST_REG_IRQ_STAT] = "IS",
+ [AHCI_HOST_REG_PORTS_IMPL] = "PI",
+ [AHCI_HOST_REG_VERSION] = "VS",
+ [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL",
+ [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS",
+ [AHCI_HOST_REG_EM_LOC] = "EM_LOC",
+ [AHCI_HOST_REG_EM_CTL] = "EM_CTL",
+ [AHCI_HOST_REG_CAP2] = "CAP2",
+ [AHCI_HOST_REG_BOHC] = "BOHC",
+};
+
+static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = {
+ [AHCI_PORT_REG_LST_ADDR] = "PxCLB",
+ [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU",
+ [AHCI_PORT_REG_FIS_ADDR] = "PxFB",
+ [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU",
+ [AHCI_PORT_REG_IRQ_STAT] = "PxIS",
+ [AHCI_PORT_REG_IRQ_MASK] = "PXIE",
+ [AHCI_PORT_REG_CMD] = "PxCMD",
+ [7] = "Reserved",
+ [AHCI_PORT_REG_TFDATA] = "PxTFD",
+ [AHCI_PORT_REG_SIG] = "PxSIG",
+ [AHCI_PORT_REG_SCR_STAT] = "PxSSTS",
+ [AHCI_PORT_REG_SCR_CTL] = "PxSCTL",
+ [AHCI_PORT_REG_SCR_ERR] = "PxSERR",
+ [AHCI_PORT_REG_SCR_ACT] = "PxSACT",
+ [AHCI_PORT_REG_CMD_ISSUE] = "PxCI",
+ [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF",
+ [AHCI_PORT_REG_FIS_CTL] = "PxFBS",
+ [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP",
+ [18 ... 27] = "Reserved",
+ [AHCI_PORT_REG_VENDOR_1 ...
+ AHCI_PORT_REG_VENDOR_4] = "PxVS",
+};
+
static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = {
[AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
[AHCI_PORT_IRQ_BIT_PSS] = "PSS",
[AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
};
-static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
+static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
{
uint32_t val;
- AHCIPortRegs *pr;
- pr = &s->dev[port].port_regs;
+ AHCIPortRegs *pr = &s->dev[port].port_regs;
+ enum AHCIPortReg regnum = offset / sizeof(uint32_t);
+ assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
- switch (offset) {
- case PORT_LST_ADDR:
+ switch (regnum) {
+ case AHCI_PORT_REG_LST_ADDR:
val = pr->lst_addr;
break;
- case PORT_LST_ADDR_HI:
+ case AHCI_PORT_REG_LST_ADDR_HI:
val = pr->lst_addr_hi;
break;
- case PORT_FIS_ADDR:
+ case AHCI_PORT_REG_FIS_ADDR:
val = pr->fis_addr;
break;
- case PORT_FIS_ADDR_HI:
+ case AHCI_PORT_REG_FIS_ADDR_HI:
val = pr->fis_addr_hi;
break;
- case PORT_IRQ_STAT:
+ case AHCI_PORT_REG_IRQ_STAT:
val = pr->irq_stat;
break;
- case PORT_IRQ_MASK:
+ case AHCI_PORT_REG_IRQ_MASK:
val = pr->irq_mask;
break;
- case PORT_CMD:
+ case AHCI_PORT_REG_CMD:
val = pr->cmd;
break;
- case PORT_TFDATA:
+ case AHCI_PORT_REG_TFDATA:
val = pr->tfdata;
break;
- case PORT_SIG:
+ case AHCI_PORT_REG_SIG:
val = pr->sig;
break;
- case PORT_SCR_STAT:
+ case AHCI_PORT_REG_SCR_STAT:
if (s->dev[port].port.ifs[0].blk) {
val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
val = SATA_SCR_SSTATUS_DET_NODEV;
}
break;
- case PORT_SCR_CTL:
+ case AHCI_PORT_REG_SCR_CTL:
val = pr->scr_ctl;
break;
- case PORT_SCR_ERR:
+ case AHCI_PORT_REG_SCR_ERR:
val = pr->scr_err;
break;
- case PORT_SCR_ACT:
+ case AHCI_PORT_REG_SCR_ACT:
val = pr->scr_act;
break;
- case PORT_CMD_ISSUE:
+ case AHCI_PORT_REG_CMD_ISSUE:
val = pr->cmd_issue;
break;
- case PORT_RESERVED:
default:
+ trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum],
+ offset);
val = 0;
}
- trace_ahci_port_read(s, port, offset, val);
+ trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val);
return val;
}
return 0;
}
-static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
+static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
{
AHCIPortRegs *pr = &s->dev[port].port_regs;
+ enum AHCIPortReg regnum = offset / sizeof(uint32_t);
+ assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
+ trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val);
- trace_ahci_port_write(s, port, offset, val);
- switch (offset) {
- case PORT_LST_ADDR:
- pr->lst_addr = val;
- break;
- case PORT_LST_ADDR_HI:
- pr->lst_addr_hi = val;
- break;
- case PORT_FIS_ADDR:
- pr->fis_addr = val;
- break;
- case PORT_FIS_ADDR_HI:
- pr->fis_addr_hi = val;
- break;
- case PORT_IRQ_STAT:
- pr->irq_stat &= ~val;
- ahci_check_irq(s);
- break;
- case PORT_IRQ_MASK:
- pr->irq_mask = val & 0xfdc000ff;
- ahci_check_irq(s);
- break;
- case PORT_CMD:
- /* Block any Read-only fields from being set;
- * including LIST_ON and FIS_ON.
- * The spec requires to set ICC bits to zero after the ICC change
- * is done. We don't support ICC state changes, therefore always
- * force the ICC bits to zero.
- */
- pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
- (val & ~(PORT_CMD_RO_MASK|PORT_CMD_ICC_MASK));
-
- /* Check FIS RX and CLB engines */
- ahci_cond_start_engines(&s->dev[port]);
-
- /* XXX usually the FIS would be pending on the bus here and
- issuing deferred until the OS enables FIS receival.
- Instead, we only submit it once - which works in most
- cases, but is a hack. */
- if ((pr->cmd & PORT_CMD_FIS_ON) &&
- !s->dev[port].init_d2h_sent) {
- ahci_init_d2h(&s->dev[port]);
- }
+ switch (regnum) {
+ case AHCI_PORT_REG_LST_ADDR:
+ pr->lst_addr = val;
+ break;
+ case AHCI_PORT_REG_LST_ADDR_HI:
+ pr->lst_addr_hi = val;
+ break;
+ case AHCI_PORT_REG_FIS_ADDR:
+ pr->fis_addr = val;
+ break;
+ case AHCI_PORT_REG_FIS_ADDR_HI:
+ pr->fis_addr_hi = val;
+ break;
+ case AHCI_PORT_REG_IRQ_STAT:
+ pr->irq_stat &= ~val;
+ ahci_check_irq(s);
+ break;
+ case AHCI_PORT_REG_IRQ_MASK:
+ pr->irq_mask = val & 0xfdc000ff;
+ ahci_check_irq(s);
+ break;
+ case AHCI_PORT_REG_CMD:
+ /* Block any Read-only fields from being set;
+ * including LIST_ON and FIS_ON.
+ * The spec requires to set ICC bits to zero after the ICC change
+ * is done. We don't support ICC state changes, therefore always
+ * force the ICC bits to zero.
+ */
+ pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
+ (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK));
+
+ /* Check FIS RX and CLB engines */
+ ahci_cond_start_engines(&s->dev[port]);
+
+ /* XXX usually the FIS would be pending on the bus here and
+ issuing deferred until the OS enables FIS receival.
+ Instead, we only submit it once - which works in most
+ cases, but is a hack. */
+ if ((pr->cmd & PORT_CMD_FIS_ON) &&
+ !s->dev[port].init_d2h_sent) {
+ ahci_init_d2h(&s->dev[port]);
+ }
- check_cmd(s, port);
- break;
- case PORT_TFDATA:
- /* Read Only. */
- break;
- case PORT_SIG:
- /* Read Only */
- break;
- case PORT_SCR_STAT:
- /* Read Only */
- break;
- case PORT_SCR_CTL:
- if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
- ((val & AHCI_SCR_SCTL_DET) == 0)) {
- ahci_reset_port(s, port);
- }
- pr->scr_ctl = val;
- break;
- case PORT_SCR_ERR:
- pr->scr_err &= ~val;
- break;
- case PORT_SCR_ACT:
- /* RW1 */
- pr->scr_act |= val;
- break;
- case PORT_CMD_ISSUE:
- pr->cmd_issue |= val;
- check_cmd(s, port);
- break;
- default:
- break;
+ check_cmd(s, port);
+ break;
+ case AHCI_PORT_REG_TFDATA:
+ case AHCI_PORT_REG_SIG:
+ case AHCI_PORT_REG_SCR_STAT:
+ /* Read Only */
+ break;
+ case AHCI_PORT_REG_SCR_CTL:
+ if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
+ ((val & AHCI_SCR_SCTL_DET) == 0)) {
+ ahci_reset_port(s, port);
+ }
+ pr->scr_ctl = val;
+ break;
+ case AHCI_PORT_REG_SCR_ERR:
+ pr->scr_err &= ~val;
+ break;
+ case AHCI_PORT_REG_SCR_ACT:
+ /* RW1 */
+ pr->scr_act |= val;
+ break;
+ case AHCI_PORT_REG_CMD_ISSUE:
+ pr->cmd_issue |= val;
+ check_cmd(s, port);
+ break;
+ default:
+ trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum],
+ offset, val);
+ qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
+ "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32,
+ port, AHCIPortReg_lookup[regnum], offset, val);
+ break;
}
}
uint32_t val = 0;
if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
- switch (addr) {
- case HOST_CAP:
+ enum AHCIHostReg regnum = addr / 4;
+ assert(regnum < AHCI_HOST_REG__COUNT);
+
+ switch (regnum) {
+ case AHCI_HOST_REG_CAP:
val = s->control_regs.cap;
break;
- case HOST_CTL:
+ case AHCI_HOST_REG_CTL:
val = s->control_regs.ghc;
break;
- case HOST_IRQ_STAT:
+ case AHCI_HOST_REG_IRQ_STAT:
val = s->control_regs.irqstatus;
break;
- case HOST_PORTS_IMPL:
+ case AHCI_HOST_REG_PORTS_IMPL:
val = s->control_regs.impl;
break;
- case HOST_VERSION:
+ case AHCI_HOST_REG_VERSION:
val = s->control_regs.version;
break;
+ default:
+ trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum],
+ addr);
}
+ trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val);
} else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
(addr < (AHCI_PORT_REGS_START_ADDR +
(s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
addr & AHCI_PORT_ADDR_OFFSET_MASK);
+ } else {
+ trace_ahci_mem_read_32_default(s, addr, val);
}
trace_ahci_mem_read_32(s, addr, val);
if (ofst + size <= 4) {
val = lo >> (ofst * 8);
} else {
- g_assert_cmpint(size, >, 1);
+ g_assert(size > 1);
/* If the 64bit read is unaligned, we will produce undefined
* results. AHCI does not support unaligned 64bit reads. */
}
if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
- switch (addr) {
- case HOST_CAP: /* R/WO, RO */
- /* FIXME handle R/WO */
- break;
- case HOST_CTL: /* R/W */
- if (val & HOST_CTL_RESET) {
- ahci_reset(s);
- } else {
- s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
- ahci_check_irq(s);
- }
- break;
- case HOST_IRQ_STAT: /* R/WC, RO */
- s->control_regs.irqstatus &= ~val;
+ enum AHCIHostReg regnum = addr / 4;
+ assert(regnum < AHCI_HOST_REG__COUNT);
+
+ switch (regnum) {
+ case AHCI_HOST_REG_CAP: /* R/WO, RO */
+ /* FIXME handle R/WO */
+ break;
+ case AHCI_HOST_REG_CTL: /* R/W */
+ if (val & HOST_CTL_RESET) {
+ ahci_reset(s);
+ } else {
+ s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
ahci_check_irq(s);
- break;
- case HOST_PORTS_IMPL: /* R/WO, RO */
- /* FIXME handle R/WO */
- break;
- case HOST_VERSION: /* RO */
- /* FIXME report write? */
- break;
- default:
- trace_ahci_mem_write_unknown(s, size, addr, val);
+ }
+ break;
+ case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */
+ s->control_regs.irqstatus &= ~val;
+ ahci_check_irq(s);
+ break;
+ case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */
+ /* FIXME handle R/WO */
+ break;
+ case AHCI_HOST_REG_VERSION: /* RO */
+ /* FIXME report write? */
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "Attempted write to unimplemented register: "
+ "AHCI host register %s, "
+ "offset 0x%"PRIx64": 0x%"PRIx64,
+ AHCIHostReg_lookup[regnum], addr, val);
+ trace_ahci_mem_write_host_unimpl(s, size,
+ AHCIHostReg_lookup[regnum], addr);
}
+ trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum],
+ addr, val);
} else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
(addr < (AHCI_PORT_REGS_START_ADDR +
- (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
+ (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
+ "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64,
+ addr, val);
+ trace_ahci_mem_write_unimpl(s, size, addr, val);
}
-
}
static const MemoryRegionOps ahci_mem_ops = {
qemu_bh_delete(ad->check_bh);
ad->check_bh = NULL;
- if ((ad->busy_slot != -1) &&
- !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
- /* no longer busy */
- ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
- ad->busy_slot = -1;
- }
-
check_cmd(ad->hba, ad->port_no);
}
}
}
-static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)
+static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i)
{
AHCIPortRegs *pr = &ad->port_regs;
uint8_t *pio_fis;
pio_fis = &ad->res_fis[RES_FIS_PSFIS];
pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
- pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
+ pio_fis[1] = (pio_fis_i ? (1 << 6) : 0);
pio_fis[2] = s->status;
pio_fis[3] = s->error;
if (pio_fis[2] & ERR_STAT) {
ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
}
-
- ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
}
static bool ahci_write_fis_d2h(AHCIDevice *ad)
d2h_fis = &ad->res_fis[RES_FIS_RFIS];
d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
- d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
+ d2h_fis[1] = (1 << 6); /* interrupt bit */
d2h_fis[2] = s->status;
d2h_fis[3] = s->error;
trace_handle_reg_h2d_fis_dump(s, port, pretty_fis);
g_free(pretty_fis);
}
- s->dev[port].done_atapi_packet = false;
- /* XXX send PIO setup FIS */
}
ide_state->error = 0;
-
+ s->dev[port].done_first_drq = false;
/* Reset transferred byte counter */
cmd->status = 0;
return 0;
}
-/* DMA dev <-> ram */
-static void ahci_start_transfer(IDEDMA *dma)
+/* Transfer PIO data between RAM and device */
+static void ahci_pio_transfer(IDEDMA *dma)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
IDEState *s = &ad->port.ifs[0];
int is_write = opts & AHCI_CMD_WRITE;
int is_atapi = opts & AHCI_CMD_ATAPI;
int has_sglist = 0;
+ bool pio_fis_i;
- if (is_atapi && !ad->done_atapi_packet) {
+ /* The PIO Setup FIS is received prior to transfer, but the interrupt
+ * is only triggered after data is received.
+ *
+ * The device only sets the 'I' bit in the PIO Setup FIS for device->host
+ * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after
+ * the first (see "DPIOO1"). The latter is consistent with the spec's
+ * description of the PACKET protocol, where the command part of ATAPI requests
+ * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests
+ * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs.
+ */
+ pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write);
+ ahci_write_fis_pio(ad, size, pio_fis_i);
+
+ if (is_atapi && !ad->done_first_drq) {
/* already prepopulated iobuffer */
- ad->done_atapi_packet = true;
- size = 0;
goto out;
}
has_sglist = 1;
}
- trace_ahci_start_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read",
- size, is_atapi ? "atapi" : "ata",
- has_sglist ? "" : "o");
+ trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read",
+ size, is_atapi ? "atapi" : "ata",
+ has_sglist ? "" : "o");
if (has_sglist && size) {
if (is_write) {
}
}
-out:
- /* declare that we processed everything */
- s->data_ptr = s->data_end;
-
/* Update number of transferred bytes, destroy sglist */
dma_buf_commit(s, size);
- s->end_transfer_func(s);
+out:
+ /* declare that we processed everything */
+ s->data_ptr = s->data_end;
- if (!(s->status & DRQ_STAT)) {
- /* done with PIO send/receive */
- ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status));
+ ad->done_first_drq = true;
+ if (pio_fis_i) {
+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
}
}
trace_ahci_cmd_done(ad->hba, ad->port_no);
+ /* no longer busy */
+ if (ad->busy_slot != -1) {
+ ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
+ ad->busy_slot = -1;
+ }
+
/* update d2h status */
ahci_write_fis_d2h(ad);
- if (!ad->check_bh) {
- /* maybe we still have something to process, check later */
+ if (ad->port_regs.cmd_issue && !ad->check_bh) {
ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
qemu_bh_schedule(ad->check_bh);
}
.start_dma = ahci_start_dma,
.restart = ahci_restart,
.restart_dma = ahci_restart_dma,
- .start_transfer = ahci_start_transfer,
+ .pio_transfer = ahci_pio_transfer,
.prepare_buf = ahci_dma_prepare_buf,
.commit_buf = ahci_commit_buf,
.rw_buf = ahci_dma_rw_buf,
VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
- VMSTATE_BOOL(done_atapi_packet, AHCIDevice),
+ VMSTATE_BOOL(done_first_drq, AHCIDevice),
VMSTATE_INT32(busy_slot, AHCIDevice),
VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS,
projects / qemu.git / blobdiff