}
}
-static TCGv __attribute__((unused)) load_fpr(DisasContext *ctx, unsigned reg)
+static TCGv load_fpr(DisasContext *ctx, unsigned reg)
{
if (likely(reg < 31)) {
return cpu_fir[reg];
}
}
-static TCGv __attribute__((unused)) dest_fpr(DisasContext *ctx, unsigned reg)
+static TCGv dest_fpr(DisasContext *ctx, unsigned reg)
{
if (likely(reg < 31)) {
return cpu_fir[reg];
static inline void gen_load_mem(DisasContext *ctx,
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
int flags),
- int ra, int rb, int32_t disp16, int fp,
- int clear)
+ int ra, int rb, int32_t disp16, bool fp,
+ bool clear)
{
- TCGv addr, va;
+ TCGv tmp, addr, va;
/* LDQ_U with ra $31 is UNOP. Other various loads are forms of
prefetches, which we can treat as nops. No worries about
return;
}
- addr = tcg_temp_new();
- if (rb != 31) {
- tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
- if (clear) {
- tcg_gen_andi_i64(addr, addr, ~0x7);
- }
- } else {
- if (clear) {
- disp16 &= ~0x7;
- }
- tcg_gen_movi_i64(addr, disp16);
+ tmp = tcg_temp_new();
+ addr = load_gpr(ctx, rb);
+
+ if (disp16) {
+ tcg_gen_addi_i64(tmp, addr, disp16);
+ addr = tmp;
+ }
+ if (clear) {
+ tcg_gen_andi_i64(tmp, addr, ~0x7);
+ addr = tmp;
}
va = (fp ? cpu_fir[ra] : cpu_ir[ra]);
tcg_gen_qemu_load(va, addr, ctx->mem_idx);
- tcg_temp_free(addr);
+ tcg_temp_free(tmp);
}
static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
static inline void gen_store_mem(DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
int flags),
- int ra, int rb, int32_t disp16, int fp,
- int clear)
+ int ra, int rb, int32_t disp16, bool fp,
+ bool clear)
{
- TCGv addr, va;
+ TCGv tmp, addr, va;
- addr = tcg_temp_new();
- if (rb != 31) {
- tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
- if (clear) {
- tcg_gen_andi_i64(addr, addr, ~0x7);
- }
- } else {
- if (clear) {
- disp16 &= ~0x7;
- }
- tcg_gen_movi_i64(addr, disp16);
- }
+ tmp = tcg_temp_new();
+ addr = load_gpr(ctx, rb);
- if (ra == 31) {
- va = tcg_const_i64(0);
- } else {
- va = (fp ? cpu_fir[ra] : cpu_ir[ra]);
+ if (disp16) {
+ tcg_gen_addi_i64(tmp, addr, disp16);
+ addr = tmp;
+ }
+ if (clear) {
+ tcg_gen_andi_i64(tmp, addr, ~0x7);
+ addr = tmp;
}
+
+ va = (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra));
tcg_gen_qemu_store(va, addr, ctx->mem_idx);
- tcg_temp_free(addr);
- if (ra == 31) {
- tcg_temp_free(va);
- }
+ tcg_temp_free(tmp);
}
static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb,
addr = tcg_temp_local_new();
#endif
- if (rb != 31) {
- tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
- } else {
- tcg_gen_movi_i64(addr, disp16);
- }
+ tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
#if defined(CONFIG_USER_ONLY)
/* ??? This is handled via a complicated version of compare-and-swap
return gen_bcond_internal(ctx, cond, cmp_tmp, disp);
}
-static void gen_cmov(TCGCond cond, int ra, int rb, int rc,
- int islit, uint8_t lit, int mask)
-{
- TCGv_i64 c1, z, v1;
-
- if (unlikely(rc == 31)) {
- return;
- }
-
- if (ra == 31) {
- /* Very uncommon case - Do not bother to optimize. */
- c1 = tcg_const_i64(0);
- } else if (mask) {
- c1 = tcg_const_i64(1);
- tcg_gen_and_i64(c1, c1, cpu_ir[ra]);
- } else {
- c1 = cpu_ir[ra];
- }
- if (islit) {
- v1 = tcg_const_i64(lit);
- } else {
- v1 = cpu_ir[rb];
- }
- z = tcg_const_i64(0);
-
- tcg_gen_movcond_i64(cond, cpu_ir[rc], c1, z, v1, cpu_ir[rc]);
-
- tcg_temp_free_i64(z);
- if (ra == 31 || mask) {
- tcg_temp_free_i64(c1);
- }
- if (islit) {
- tcg_temp_free_i64(v1);
- }
-}
-
static void gen_fcmov(TCGCond cond, int ra, int rb, int rc)
{
TCGv_i64 c1, z, v1;
gen_fcvtql(rb, rc);
}
-#define FARITH2(name) \
- static inline void glue(gen_f, name)(int rb, int rc) \
- { \
- if (unlikely(rc == 31)) { \
- return; \
- } \
- if (rb != 31) { \
- gen_helper_ ## name(cpu_fir[rc], cpu_env, cpu_fir[rb]); \
- } else { \
- TCGv tmp = tcg_const_i64(0); \
- gen_helper_ ## name(cpu_fir[rc], cpu_env, tmp); \
- tcg_temp_free(tmp); \
- } \
- }
-
-/* ??? VAX instruction qualifiers ignored. */
-FARITH2(sqrtf)
-FARITH2(sqrtg)
-FARITH2(cvtgf)
-FARITH2(cvtgq)
-FARITH2(cvtqf)
-FARITH2(cvtqg)
-
static void gen_ieee_arith2(DisasContext *ctx,
void (*helper)(TCGv, TCGv_ptr, TCGv),
int rb, int rc, int fn11)
gen_cpys_internal(ra, rb, rc, 0, 0xFFF0000000000000ULL);
}
-#define FARITH3(name) \
- static inline void glue(gen_f, name)(int ra, int rb, int rc) \
- { \
- TCGv va, vb; \
- \
- if (unlikely(rc == 31)) { \
- return; \
- } \
- if (ra == 31) { \
- va = tcg_const_i64(0); \
- } else { \
- va = cpu_fir[ra]; \
- } \
- if (rb == 31) { \
- vb = tcg_const_i64(0); \
- } else { \
- vb = cpu_fir[rb]; \
- } \
- \
- gen_helper_ ## name(cpu_fir[rc], cpu_env, va, vb); \
- \
- if (ra == 31) { \
- tcg_temp_free(va); \
- } \
- if (rb == 31) { \
- tcg_temp_free(vb); \
- } \
- }
-
-/* ??? VAX instruction qualifiers ignored. */
-FARITH3(addf)
-FARITH3(subf)
-FARITH3(mulf)
-FARITH3(divf)
-FARITH3(addg)
-FARITH3(subg)
-FARITH3(mulg)
-FARITH3(divg)
-FARITH3(cmpgeq)
-FARITH3(cmpglt)
-FARITH3(cmpgle)
-
static void gen_ieee_arith3(DisasContext *ctx,
void (*helper)(TCGv, TCGv_ptr, TCGv, TCGv),
int ra, int rb, int rc, int fn11)
tcg_gen_mov_i64(dest, src);
break;
default:
- tcg_gen_andi_i64 (dest, src, zapnot_mask (lit));
+ tcg_gen_andi_i64(dest, src, zapnot_mask(lit));
break;
}
}
-static inline void gen_zapnot(int ra, int rb, int rc, int islit, uint8_t lit)
-{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- gen_zapnoti(cpu_ir[rc], cpu_ir[ra], lit);
- } else {
- gen_helper_zapnot (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
-}
-
-static inline void gen_zap(int ra, int rb, int rc, int islit, uint8_t lit)
-{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- gen_zapnoti(cpu_ir[rc], cpu_ir[ra], ~lit);
- } else {
- gen_helper_zap (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
-}
-
-
/* EXTWH, EXTLH, EXTQH */
-static void gen_ext_h(int ra, int rb, int rc, int islit,
+static void gen_ext_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
+ if (islit) {
+ tcg_gen_shli_i64(vc, va, (64 - lit * 8) & 0x3f);
} else {
- if (islit) {
- lit = (64 - (lit & 7) * 8) & 0x3f;
- tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit);
- } else {
- TCGv tmp1 = tcg_temp_new();
- tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
- tcg_gen_shli_i64(tmp1, tmp1, 3);
- tcg_gen_neg_i64(tmp1, tmp1);
- tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
- tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
- tcg_temp_free(tmp1);
- }
- gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask);
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_shli_i64(tmp, load_gpr(ctx, rb), 3);
+ tcg_gen_neg_i64(tmp, tmp);
+ tcg_gen_andi_i64(tmp, tmp, 0x3f);
+ tcg_gen_shl_i64(vc, va, tmp);
+ tcg_temp_free(tmp);
}
+ gen_zapnoti(vc, vc, byte_mask);
}
/* EXTBL, EXTWL, EXTLL, EXTQL */
-static void gen_ext_l(int ra, int rb, int rc, int islit,
+static void gen_ext_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
+ if (islit) {
+ tcg_gen_shri_i64(vc, va, (lit & 7) * 8);
} else {
- if (islit) {
- tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
- } else {
- TCGv tmp = tcg_temp_new();
- tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
- tcg_gen_shli_i64(tmp, tmp, 3);
- tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
- tcg_temp_free(tmp);
- }
- gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask);
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_andi_i64(tmp, load_gpr(ctx, rb), 7);
+ tcg_gen_shli_i64(tmp, tmp, 3);
+ tcg_gen_shr_i64(vc, va, tmp);
+ tcg_temp_free(tmp);
}
+ gen_zapnoti(vc, vc, byte_mask);
}
/* INSWH, INSLH, INSQH */
-static void gen_ins_h(int ra, int rb, int rc, int islit,
+static void gen_ins_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31) || (islit && (lit & 7) == 0)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else {
- TCGv tmp = tcg_temp_new();
+ TCGv tmp = tcg_temp_new();
- /* The instruction description has us left-shift the byte mask
- and extract bits <15:8> and apply that zap at the end. This
- is equivalent to simply performing the zap first and shifting
- afterward. */
- gen_zapnoti (tmp, cpu_ir[ra], byte_mask);
+ /* The instruction description has us left-shift the byte mask and extract
+ bits <15:8> and apply that zap at the end. This is equivalent to simply
+ performing the zap first and shifting afterward. */
+ gen_zapnoti(tmp, va, byte_mask);
- if (islit) {
- /* Note that we have handled the lit==0 case above. */
- tcg_gen_shri_i64 (cpu_ir[rc], tmp, 64 - (lit & 7) * 8);
+ if (islit) {
+ lit &= 7;
+ if (unlikely(lit == 0)) {
+ tcg_gen_movi_i64(vc, 0);
} else {
- TCGv shift = tcg_temp_new();
-
- /* If (B & 7) == 0, we need to shift by 64 and leave a zero.
- Do this portably by splitting the shift into two parts:
- shift_count-1 and 1. Arrange for the -1 by using
- ones-complement instead of twos-complement in the negation:
- ~((B & 7) * 8) & 63. */
-
- tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
- tcg_gen_shli_i64(shift, shift, 3);
- tcg_gen_not_i64(shift, shift);
- tcg_gen_andi_i64(shift, shift, 0x3f);
-
- tcg_gen_shr_i64(cpu_ir[rc], tmp, shift);
- tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[rc], 1);
- tcg_temp_free(shift);
+ tcg_gen_shri_i64(vc, tmp, 64 - lit * 8);
}
- tcg_temp_free(tmp);
+ } else {
+ TCGv shift = tcg_temp_new();
+
+ /* If (B & 7) == 0, we need to shift by 64 and leave a zero. Do this
+ portably by splitting the shift into two parts: shift_count-1 and 1.
+ Arrange for the -1 by using ones-complement instead of
+ twos-complement in the negation: ~(B * 8) & 63. */
+
+ tcg_gen_shli_i64(shift, load_gpr(ctx, rb), 3);
+ tcg_gen_not_i64(shift, shift);
+ tcg_gen_andi_i64(shift, shift, 0x3f);
+
+ tcg_gen_shr_i64(vc, tmp, shift);
+ tcg_gen_shri_i64(vc, vc, 1);
+ tcg_temp_free(shift);
}
+ tcg_temp_free(tmp);
}
/* INSBL, INSWL, INSLL, INSQL */
-static void gen_ins_l(int ra, int rb, int rc, int islit,
+static void gen_ins_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else {
- TCGv tmp = tcg_temp_new();
+ TCGv tmp = tcg_temp_new();
- /* The instruction description has us left-shift the byte mask
- the same number of byte slots as the data and apply the zap
- at the end. This is equivalent to simply performing the zap
- first and shifting afterward. */
- gen_zapnoti (tmp, cpu_ir[ra], byte_mask);
+ /* The instruction description has us left-shift the byte mask
+ the same number of byte slots as the data and apply the zap
+ at the end. This is equivalent to simply performing the zap
+ first and shifting afterward. */
+ gen_zapnoti(tmp, va, byte_mask);
- if (islit) {
- tcg_gen_shli_i64(cpu_ir[rc], tmp, (lit & 7) * 8);
- } else {
- TCGv shift = tcg_temp_new();
- tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
- tcg_gen_shli_i64(shift, shift, 3);
- tcg_gen_shl_i64(cpu_ir[rc], tmp, shift);
- tcg_temp_free(shift);
- }
- tcg_temp_free(tmp);
+ if (islit) {
+ tcg_gen_shli_i64(vc, tmp, (lit & 7) * 8);
+ } else {
+ TCGv shift = tcg_temp_new();
+ tcg_gen_andi_i64(shift, load_gpr(ctx, rb), 7);
+ tcg_gen_shli_i64(shift, shift, 3);
+ tcg_gen_shl_i64(vc, tmp, shift);
+ tcg_temp_free(shift);
}
+ tcg_temp_free(tmp);
}
/* MSKWH, MSKLH, MSKQH */
-static void gen_msk_h(int ra, int rb, int rc, int islit,
+static void gen_msk_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8));
+ if (islit) {
+ gen_zapnoti(vc, va, ~((byte_mask << (lit & 7)) >> 8));
} else {
TCGv shift = tcg_temp_new();
TCGv mask = tcg_temp_new();
shift of 64 bits in order to generate a zero. This is done by
splitting the shift into two parts, the variable shift - 1
followed by a constant 1 shift. The code we expand below is
- equivalent to ~((B & 7) * 8) & 63. */
+ equivalent to ~(B * 8) & 63. */
- tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
- tcg_gen_shli_i64(shift, shift, 3);
+ tcg_gen_shli_i64(shift, load_gpr(ctx, rb), 3);
tcg_gen_not_i64(shift, shift);
tcg_gen_andi_i64(shift, shift, 0x3f);
tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
tcg_gen_shr_i64(mask, mask, shift);
tcg_gen_shri_i64(mask, mask, 1);
- tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
+ tcg_gen_andc_i64(vc, va, mask);
tcg_temp_free(mask);
tcg_temp_free(shift);
}
/* MSKBL, MSKWL, MSKLL, MSKQL */
-static void gen_msk_l(int ra, int rb, int rc, int islit,
+static void gen_msk_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit,
uint8_t lit, uint8_t byte_mask)
{
- if (unlikely(rc == 31)) {
- return;
- } else if (unlikely(ra == 31)) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~(byte_mask << (lit & 7)));
+ if (islit) {
+ gen_zapnoti(vc, va, ~(byte_mask << (lit & 7)));
} else {
TCGv shift = tcg_temp_new();
TCGv mask = tcg_temp_new();
- tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
+ tcg_gen_andi_i64(shift, load_gpr(ctx, rb), 7);
tcg_gen_shli_i64(shift, shift, 3);
- tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
+ tcg_gen_movi_i64(mask, zapnot_mask(byte_mask));
tcg_gen_shl_i64(mask, mask, shift);
- tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
+ tcg_gen_andc_i64(vc, va, mask);
tcg_temp_free(mask);
tcg_temp_free(shift);
}
}
-/* Code to call arith3 helpers */
-#define ARITH3(name) \
-static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
- uint8_t lit) \
-{ \
- if (unlikely(rc == 31)) \
- return; \
- \
- if (ra != 31) { \
- if (islit) { \
- TCGv tmp = tcg_const_i64(lit); \
- gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \
- tcg_temp_free(tmp); \
- } else \
- gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \
- } else { \
- TCGv tmp1 = tcg_const_i64(0); \
- if (islit) { \
- TCGv tmp2 = tcg_const_i64(lit); \
- gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \
- tcg_temp_free(tmp2); \
- } else \
- gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \
- tcg_temp_free(tmp1); \
- } \
-}
-ARITH3(cmpbge)
-ARITH3(minub8)
-ARITH3(minsb8)
-ARITH3(minuw4)
-ARITH3(minsw4)
-ARITH3(maxub8)
-ARITH3(maxsb8)
-ARITH3(maxuw4)
-ARITH3(maxsw4)
-ARITH3(perr)
-
-/* Code to call arith3 helpers */
-#define ARITH3_EX(name) \
- static inline void glue(gen_, name)(int ra, int rb, int rc, \
- int islit, uint8_t lit) \
- { \
- if (unlikely(rc == 31)) { \
- return; \
- } \
- if (ra != 31) { \
- if (islit) { \
- TCGv tmp = tcg_const_i64(lit); \
- gen_helper_ ## name(cpu_ir[rc], cpu_env, \
- cpu_ir[ra], tmp); \
- tcg_temp_free(tmp); \
- } else { \
- gen_helper_ ## name(cpu_ir[rc], cpu_env, \
- cpu_ir[ra], cpu_ir[rb]); \
- } \
- } else { \
- TCGv tmp1 = tcg_const_i64(0); \
- if (islit) { \
- TCGv tmp2 = tcg_const_i64(lit); \
- gen_helper_ ## name(cpu_ir[rc], cpu_env, tmp1, tmp2); \
- tcg_temp_free(tmp2); \
- } else { \
- gen_helper_ ## name(cpu_ir[rc], cpu_env, tmp1, cpu_ir[rb]); \
- } \
- tcg_temp_free(tmp1); \
- } \
- }
-ARITH3_EX(addlv)
-ARITH3_EX(sublv)
-ARITH3_EX(addqv)
-ARITH3_EX(subqv)
-ARITH3_EX(mullv)
-ARITH3_EX(mulqv)
-
#define MVIOP2(name) \
static inline void glue(gen_, name)(int rb, int rc) \
{ \
MVIOP2(unpkbl)
MVIOP2(unpkbw)
-static void gen_cmp(TCGCond cond, int ra, int rb, int rc,
- int islit, uint8_t lit)
-{
- TCGv va, vb;
-
- if (unlikely(rc == 31)) {
- return;
- }
-
- if (ra == 31) {
- va = tcg_const_i64(0);
- } else {
- va = cpu_ir[ra];
- }
- if (islit) {
- vb = tcg_const_i64(lit);
- } else {
- vb = cpu_ir[rb];
- }
-
- tcg_gen_setcond_i64(cond, cpu_ir[rc], va, vb);
-
- if (ra == 31) {
- tcg_temp_free(va);
- }
- if (islit) {
- tcg_temp_free(vb);
- }
-}
-
static void gen_rx(int ra, int set)
{
TCGv_i32 tmp;
uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
bool islit;
TCGv va, vb, vc, tmp;
+ TCGv_i32 t32;
ExitStatus ret;
/* Decode all instruction fields */
break;
case 0x0F:
/* CMPBGE */
- gen_cmpbge(ra, rb, rc, islit, lit);
+ gen_helper_cmpbge(vc, va, vb);
break;
case 0x12:
/* S8ADDL */
break;
case 0x1D:
/* CMPULT */
- gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
+ tcg_gen_setcond_i64(TCG_COND_LTU, vc, va, vb);
break;
case 0x20:
/* ADDQ */
break;
case 0x2D:
/* CMPEQ */
- gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
+ tcg_gen_setcond_i64(TCG_COND_EQ, vc, va, vb);
break;
case 0x32:
/* S8ADDQ */
break;
case 0x3D:
/* CMPULE */
- gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
+ tcg_gen_setcond_i64(TCG_COND_LEU, vc, va, vb);
break;
case 0x40:
/* ADDL/V */
- gen_addlv(ra, rb, rc, islit, lit);
+ gen_helper_addlv(vc, cpu_env, va, vb);
break;
case 0x49:
/* SUBL/V */
- gen_sublv(ra, rb, rc, islit, lit);
+ gen_helper_sublv(vc, cpu_env, va, vb);
break;
case 0x4D:
/* CMPLT */
- gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
+ tcg_gen_setcond_i64(TCG_COND_LT, vc, va, vb);
break;
case 0x60:
/* ADDQ/V */
- gen_addqv(ra, rb, rc, islit, lit);
+ gen_helper_addqv(vc, cpu_env, va, vb);
break;
case 0x69:
/* SUBQ/V */
- gen_subqv(ra, rb, rc, islit, lit);
+ gen_helper_subqv(vc, cpu_env, va, vb);
break;
case 0x6D:
/* CMPLE */
- gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
+ tcg_gen_setcond_i64(TCG_COND_LE, vc, va, vb);
break;
default:
goto invalid_opc;
break;
case 0x14:
/* CMOVLBS */
- gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i64(tmp, va, 1);
+ tcg_gen_movcond_i64(TCG_COND_NE, vc, tmp, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
+ tcg_temp_free(tmp);
break;
case 0x16:
/* CMOVLBC */
- gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i64(tmp, va, 1);
+ tcg_gen_movcond_i64(TCG_COND_EQ, vc, tmp, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
+ tcg_temp_free(tmp);
break;
case 0x20:
/* BIS */
break;
case 0x24:
/* CMOVEQ */
- gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, vc, va, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
break;
case 0x26:
/* CMOVNE */
- gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
+ tcg_gen_movcond_i64(TCG_COND_NE, vc, va, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
break;
case 0x28:
/* ORNOT */
break;
case 0x44:
/* CMOVLT */
- gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
+ tcg_gen_movcond_i64(TCG_COND_LT, vc, va, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
break;
case 0x46:
/* CMOVGE */
- gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
+ tcg_gen_movcond_i64(TCG_COND_GE, vc, va, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
break;
case 0x48:
/* EQV */
break;
case 0x64:
/* CMOVLE */
- gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
+ tcg_gen_movcond_i64(TCG_COND_LE, vc, va, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
break;
case 0x66:
/* CMOVGT */
- gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
+ tcg_gen_movcond_i64(TCG_COND_GT, vc, va, load_zero(ctx),
+ vb, load_gpr(ctx, rc));
break;
case 0x6C:
/* IMPLVER */
goto invalid_opc;
}
break;
+
case 0x12:
+ vc = dest_gpr(ctx, rc);
+ va = load_gpr(ctx, ra);
switch (fn7) {
case 0x02:
/* MSKBL */
- gen_msk_l(ra, rb, rc, islit, lit, 0x01);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x06:
/* EXTBL */
- gen_ext_l(ra, rb, rc, islit, lit, 0x01);
+ gen_ext_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x0B:
/* INSBL */
- gen_ins_l(ra, rb, rc, islit, lit, 0x01);
+ gen_ins_l(ctx, vc, va, rb, islit, lit, 0x01);
break;
case 0x12:
/* MSKWL */
- gen_msk_l(ra, rb, rc, islit, lit, 0x03);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x16:
/* EXTWL */
- gen_ext_l(ra, rb, rc, islit, lit, 0x03);
+ gen_ext_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x1B:
/* INSWL */
- gen_ins_l(ra, rb, rc, islit, lit, 0x03);
+ gen_ins_l(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x22:
/* MSKLL */
- gen_msk_l(ra, rb, rc, islit, lit, 0x0f);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x26:
/* EXTLL */
- gen_ext_l(ra, rb, rc, islit, lit, 0x0f);
+ gen_ext_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x2B:
/* INSLL */
- gen_ins_l(ra, rb, rc, islit, lit, 0x0f);
+ gen_ins_l(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x30:
/* ZAP */
- gen_zap(ra, rb, rc, islit, lit);
+ if (islit) {
+ gen_zapnoti(vc, va, ~lit);
+ } else {
+ gen_helper_zap(vc, va, load_gpr(ctx, rb));
+ }
break;
case 0x31:
/* ZAPNOT */
- gen_zapnot(ra, rb, rc, islit, lit);
+ if (islit) {
+ gen_zapnoti(vc, va, lit);
+ } else {
+ gen_helper_zapnot(vc, va, load_gpr(ctx, rb));
+ }
break;
case 0x32:
/* MSKQL */
- gen_msk_l(ra, rb, rc, islit, lit, 0xff);
+ gen_msk_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x34:
/* SRL */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
- } else {
- TCGv shift = tcg_temp_new();
- tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
- tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
- tcg_temp_free(shift);
- }
- } else
- tcg_gen_movi_i64(cpu_ir[rc], 0);
+ if (islit) {
+ tcg_gen_shri_i64(vc, va, lit & 0x3f);
+ } else {
+ tmp = tcg_temp_new();
+ vb = load_gpr(ctx, rb);
+ tcg_gen_andi_i64(tmp, vb, 0x3f);
+ tcg_gen_shr_i64(vc, va, tmp);
+ tcg_temp_free(tmp);
}
break;
case 0x36:
/* EXTQL */
- gen_ext_l(ra, rb, rc, islit, lit, 0xff);
+ gen_ext_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x39:
/* SLL */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
- } else {
- TCGv shift = tcg_temp_new();
- tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
- tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
- tcg_temp_free(shift);
- }
- } else
- tcg_gen_movi_i64(cpu_ir[rc], 0);
+ if (islit) {
+ tcg_gen_shli_i64(vc, va, lit & 0x3f);
+ } else {
+ tmp = tcg_temp_new();
+ vb = load_gpr(ctx, rb);
+ tcg_gen_andi_i64(tmp, vb, 0x3f);
+ tcg_gen_shl_i64(vc, va, tmp);
+ tcg_temp_free(tmp);
}
break;
case 0x3B:
/* INSQL */
- gen_ins_l(ra, rb, rc, islit, lit, 0xff);
+ gen_ins_l(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x3C:
/* SRA */
- if (likely(rc != 31)) {
- if (ra != 31) {
- if (islit) {
- tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
- } else {
- TCGv shift = tcg_temp_new();
- tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
- tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
- tcg_temp_free(shift);
- }
- } else
- tcg_gen_movi_i64(cpu_ir[rc], 0);
+ if (islit) {
+ tcg_gen_sari_i64(vc, va, lit & 0x3f);
+ } else {
+ tmp = tcg_temp_new();
+ vb = load_gpr(ctx, rb);
+ tcg_gen_andi_i64(tmp, vb, 0x3f);
+ tcg_gen_sar_i64(vc, va, tmp);
+ tcg_temp_free(tmp);
}
break;
case 0x52:
/* MSKWH */
- gen_msk_h(ra, rb, rc, islit, lit, 0x03);
+ gen_msk_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x57:
/* INSWH */
- gen_ins_h(ra, rb, rc, islit, lit, 0x03);
+ gen_ins_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x5A:
/* EXTWH */
- gen_ext_h(ra, rb, rc, islit, lit, 0x03);
+ gen_ext_h(ctx, vc, va, rb, islit, lit, 0x03);
break;
case 0x62:
/* MSKLH */
- gen_msk_h(ra, rb, rc, islit, lit, 0x0f);
+ gen_msk_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x67:
/* INSLH */
- gen_ins_h(ra, rb, rc, islit, lit, 0x0f);
+ gen_ins_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x6A:
/* EXTLH */
- gen_ext_h(ra, rb, rc, islit, lit, 0x0f);
+ gen_ext_h(ctx, vc, va, rb, islit, lit, 0x0f);
break;
case 0x72:
/* MSKQH */
- gen_msk_h(ra, rb, rc, islit, lit, 0xff);
+ gen_msk_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x77:
/* INSQH */
- gen_ins_h(ra, rb, rc, islit, lit, 0xff);
+ gen_ins_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
case 0x7A:
/* EXTQH */
- gen_ext_h(ra, rb, rc, islit, lit, 0xff);
+ gen_ext_h(ctx, vc, va, rb, islit, lit, 0xff);
break;
default:
goto invalid_opc;
}
break;
+
case 0x13:
+ vc = dest_gpr(ctx, rc);
+ vb = load_gpr_lit(ctx, rb, lit, islit);
+ va = load_gpr(ctx, ra);
switch (fn7) {
case 0x00:
/* MULL */
- if (likely(rc != 31)) {
- if (ra == 31) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else {
- if (islit) {
- tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
- } else {
- tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
- }
- }
+ tcg_gen_mul_i64(vc, va, vb);
+ tcg_gen_ext32s_i64(vc, vc);
break;
case 0x20:
/* MULQ */
- if (likely(rc != 31)) {
- if (ra == 31) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- } else if (islit) {
- tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
- } else {
- tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- }
+ tcg_gen_mul_i64(vc, va, vb);
break;
case 0x30:
/* UMULH */
- {
- TCGv low;
- if (unlikely(rc == 31)){
- break;
- }
- if (ra == 31) {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- break;
- }
- low = tcg_temp_new();
- if (islit) {
- tcg_gen_movi_tl(low, lit);
- tcg_gen_mulu2_i64(low, cpu_ir[rc], cpu_ir[ra], low);
- } else {
- tcg_gen_mulu2_i64(low, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
- }
- tcg_temp_free(low);
- }
+ tmp = tcg_temp_new();
+ tcg_gen_mulu2_i64(tmp, vc, va, vb);
+ tcg_temp_free(tmp);
break;
case 0x40:
/* MULL/V */
- gen_mullv(ra, rb, rc, islit, lit);
+ gen_helper_mullv(vc, cpu_env, va, vb);
break;
case 0x60:
/* MULQ/V */
- gen_mulqv(ra, rb, rc, islit, lit);
+ gen_helper_mulqv(vc, cpu_env, va, vb);
break;
default:
goto invalid_opc;
}
break;
+
case 0x14:
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
+ vc = dest_fpr(ctx, rc);
switch (fpfn) { /* fn11 & 0x3F */
case 0x04:
/* ITOFS */
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
- gen_helper_memory_to_s(cpu_fir[rc], tmp);
- tcg_temp_free_i32(tmp);
- } else
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- }
+ t32 = tcg_temp_new_i32();
+ va = load_gpr(ctx, ra);
+ tcg_gen_trunc_i64_i32(t32, va);
+ gen_helper_memory_to_s(vc, t32);
+ tcg_temp_free_i32(t32);
break;
case 0x0A:
/* SQRTF */
REQUIRE_REG_31(ra);
- gen_fsqrtf(rb, rc);
+ vb = load_fpr(ctx, rb);
+ gen_helper_sqrtf(vc, cpu_env, vb);
break;
case 0x0B:
/* SQRTS */
case 0x14:
/* ITOFF */
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
- gen_helper_memory_to_f(cpu_fir[rc], tmp);
- tcg_temp_free_i32(tmp);
- } else
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- }
+ t32 = tcg_temp_new_i32();
+ va = load_gpr(ctx, ra);
+ tcg_gen_trunc_i64_i32(t32, va);
+ gen_helper_memory_to_f(vc, t32);
+ tcg_temp_free_i32(t32);
break;
case 0x24:
/* ITOFT */
REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]);
- } else {
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- }
- }
+ va = load_gpr(ctx, ra);
+ tcg_gen_mov_i64(vc, va);
break;
case 0x2A:
/* SQRTG */
REQUIRE_REG_31(ra);
- gen_fsqrtg(rb, rc);
+ vb = load_fpr(ctx, rb);
+ gen_helper_sqrtg(vc, cpu_env, vb);
break;
case 0x02B:
/* SQRTT */
goto invalid_opc;
}
break;
+
case 0x15:
/* VAX floating point */
/* XXX: rounding mode and trap are ignored (!) */
+ vc = dest_fpr(ctx, rc);
+ vb = load_fpr(ctx, rb);
+ va = load_fpr(ctx, ra);
switch (fpfn) { /* fn11 & 0x3F */
case 0x00:
/* ADDF */
- gen_faddf(ra, rb, rc);
+ gen_helper_addf(vc, cpu_env, va, vb);
break;
case 0x01:
/* SUBF */
- gen_fsubf(ra, rb, rc);
+ gen_helper_subf(vc, cpu_env, va, vb);
break;
case 0x02:
/* MULF */
- gen_fmulf(ra, rb, rc);
+ gen_helper_mulf(vc, cpu_env, va, vb);
break;
case 0x03:
/* DIVF */
- gen_fdivf(ra, rb, rc);
+ gen_helper_divf(vc, cpu_env, va, vb);
break;
case 0x1E:
/* CVTDG -- TODO */
goto invalid_opc;
case 0x20:
/* ADDG */
- gen_faddg(ra, rb, rc);
+ gen_helper_addg(vc, cpu_env, va, vb);
break;
case 0x21:
/* SUBG */
- gen_fsubg(ra, rb, rc);
+ gen_helper_subg(vc, cpu_env, va, vb);
break;
case 0x22:
/* MULG */
- gen_fmulg(ra, rb, rc);
+ gen_helper_mulg(vc, cpu_env, va, vb);
break;
case 0x23:
/* DIVG */
- gen_fdivg(ra, rb, rc);
+ gen_helper_divg(vc, cpu_env, va, vb);
break;
case 0x25:
/* CMPGEQ */
- gen_fcmpgeq(ra, rb, rc);
+ gen_helper_cmpgeq(vc, cpu_env, va, vb);
break;
case 0x26:
/* CMPGLT */
- gen_fcmpglt(ra, rb, rc);
+ gen_helper_cmpglt(vc, cpu_env, va, vb);
break;
case 0x27:
/* CMPGLE */
- gen_fcmpgle(ra, rb, rc);
+ gen_helper_cmpgle(vc, cpu_env, va, vb);
break;
case 0x2C:
/* CVTGF */
REQUIRE_REG_31(ra);
- gen_fcvtgf(rb, rc);
+ gen_helper_cvtgf(vc, cpu_env, vb);
break;
case 0x2D:
/* CVTGD -- TODO */
case 0x2F:
/* CVTGQ */
REQUIRE_REG_31(ra);
- gen_fcvtgq(rb, rc);
+ gen_helper_cvtgq(vc, cpu_env, vb);
break;
case 0x3C:
/* CVTQF */
REQUIRE_REG_31(ra);
- gen_fcvtqf(rb, rc);
+ gen_helper_cvtqf(vc, cpu_env, vb);
break;
case 0x3E:
/* CVTQG */
REQUIRE_REG_31(ra);
- gen_fcvtqg(rb, rc);
+ gen_helper_cvtqg(vc, cpu_env, vb);
break;
default:
goto invalid_opc;
}
break;
+
case 0x16:
/* IEEE floating-point */
switch (fpfn) { /* fn11 & 0x3F */
goto invalid_opc;
}
break;
+
case 0x17:
switch (fn11) {
case 0x010:
gen_fcvtlq(rb, rc);
break;
case 0x020:
- if (likely(rc != 31)) {
- if (ra == rb) {
- /* FMOV */
- if (ra == 31) {
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- } else {
- tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);
- }
+ /* CPYS */
+ if (rc == 31) {
+ /* Special case CPYS as FNOP. */
+ } else if (ra == rb) {
+ vc = dest_fpr(ctx, rc);
+ /* Special case CPYS as FMOV. */
+ if (ra == 31) {
+ tcg_gen_movi_i64(vc, 0);
} else {
- /* CPYS */
- gen_fcpys(ra, rb, rc);
+ va = load_fpr(ctx, ra);
+ tcg_gen_mov_i64(vc, va);
}
+ } else {
+ gen_fcpys(ra, rb, rc);
}
break;
case 0x021:
break;
case 0x024:
/* MT_FPCR */
- if (likely(ra != 31)) {
- gen_helper_store_fpcr(cpu_env, cpu_fir[ra]);
- } else {
- TCGv tmp = tcg_const_i64(0);
- gen_helper_store_fpcr(cpu_env, tmp);
- tcg_temp_free(tmp);
- }
+ va = load_fpr(ctx, ra);
+ gen_helper_store_fpcr(cpu_env, va);
break;
case 0x025:
/* MF_FPCR */
- if (likely(ra != 31)) {
- gen_helper_load_fpcr(cpu_fir[ra], cpu_env);
- }
+ va = dest_fpr(ctx, ra);
+ gen_helper_load_fpcr(va, cpu_env);
break;
case 0x02A:
/* FCMOVEQ */
goto invalid_opc;
}
break;
+
case 0x18:
switch ((uint16_t)disp16) {
case 0x0000:
break;
case 0xC000:
/* RPCC */
- if (ra != 31) {
- if (use_icount) {
- gen_io_start();
- gen_helper_load_pcc(cpu_ir[ra], cpu_env);
- gen_io_end();
- ret = EXIT_PC_STALE;
- } else {
- gen_helper_load_pcc(cpu_ir[ra], cpu_env);
- }
+ va = dest_gpr(ctx, ra);
+ if (use_icount) {
+ gen_io_start();
+ gen_helper_load_pcc(va, cpu_env);
+ gen_io_end();
+ ret = EXIT_PC_STALE;
+ } else {
+ gen_helper_load_pcc(va, cpu_env);
}
break;
case 0xE000:
goto invalid_opc;
}
break;
+
case 0x19:
/* HW_MFPR (PALcode) */
#ifndef CONFIG_USER_ONLY
#else
goto invalid_opc;
#endif
+
case 0x1A:
/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
prediction stack action, which of course we don't implement. */
- if (rb != 31) {
- tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
- } else {
- tcg_gen_movi_i64(cpu_pc, 0);
- }
+ vb = load_gpr(ctx, rb);
+ tcg_gen_andi_i64(cpu_pc, vb, ~3);
if (ra != 31) {
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
}
ret = EXIT_PC_UPDATED;
break;
+
case 0x1B:
/* HW_LD (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);
{
- TCGv addr;
+ TCGv addr = tcg_temp_new();
+ vb = load_gpr(ctx, rb);
+ va = dest_gpr(ctx, ra);
- if (ra == 31) {
- break;
- }
-
- addr = tcg_temp_new();
- if (rb != 31) {
- tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
- } else {
- tcg_gen_movi_i64(addr, disp12);
- }
+ tcg_gen_addi_i64(addr, vb, disp12);
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
- gen_helper_ldl_phys(cpu_ir[ra], cpu_env, addr);
+ gen_helper_ldl_phys(va, cpu_env, addr);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
- gen_helper_ldq_phys(cpu_ir[ra], cpu_env, addr);
+ gen_helper_ldq_phys(va, cpu_env, addr);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
- gen_helper_ldl_l_phys(cpu_ir[ra], cpu_env, addr);
+ gen_helper_ldl_l_phys(va, cpu_env, addr);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
- gen_helper_ldq_l_phys(cpu_ir[ra], cpu_env, addr);
+ gen_helper_ldq_l_phys(va, cpu_env, addr);
break;
case 0x4:
/* Longword virtual PTE fetch (hw_ldl/v) */
goto invalid_opc;
case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */
- tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_KERNEL_IDX, MO_LESL);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL);
break;
case 0xB:
/* Quadword virtual access with protection check (hw_ldq/w) */
- tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_KERNEL_IDX, MO_LEQ);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEQ);
break;
case 0xC:
/* Longword virtual access with alt access mode (hw_ldl/a)*/
case 0xE:
/* Longword virtual access with alternate access mode and
protection checks (hw_ldl/wa) */
- tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_USER_IDX, MO_LESL);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL);
break;
case 0xF:
/* Quadword virtual access with alternate access mode and
protection checks (hw_ldq/wa) */
- tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_USER_IDX, MO_LEQ);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEQ);
break;
}
tcg_temp_free(addr);
#else
goto invalid_opc;
#endif
+
case 0x1C:
+ vc = dest_gpr(ctx, rc);
+ if (fn7 == 0x70) {
+ /* FTOIT */
+ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
+ REQUIRE_REG_31(rb);
+ va = load_fpr(ctx, ra);
+ tcg_gen_mov_i64(vc, va);
+ break;
+ } else if (fn7 == 0x78) {
+ /* FTOIS */
+ REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
+ REQUIRE_REG_31(rb);
+ t32 = tcg_temp_new_i32();
+ va = load_fpr(ctx, ra);
+ gen_helper_s_to_memory(t32, va);
+ tcg_gen_ext_i32_i64(vc, t32);
+ tcg_temp_free_i32(t32);
+ break;
+ }
+
+ vb = load_gpr_lit(ctx, rb, lit, islit);
switch (fn7) {
case 0x00:
/* SEXTB */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
- } else {
- tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ tcg_gen_ext8s_i64(vc, vb);
break;
case 0x01:
/* SEXTW */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
- } else {
- tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ tcg_gen_ext16s_i64(vc, vb);
break;
case 0x30:
/* CTPOP */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
- } else {
- gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ gen_helper_ctpop(vc, vb);
break;
case 0x31:
/* PERR */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_perr(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_perr(vc, va, vb);
break;
case 0x32:
/* CTLZ */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
- } else {
- gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ gen_helper_ctlz(vc, vb);
break;
case 0x33:
/* CTTZ */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);
REQUIRE_REG_31(ra);
- if (likely(rc != 31)) {
- if (islit) {
- tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
- } else {
- gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]);
- }
- }
+ gen_helper_cttz(vc, vb);
break;
case 0x34:
/* UNPKBW */
case 0x38:
/* MINSB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_minsb8(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_minsb8(vc, va, vb);
break;
case 0x39:
/* MINSW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_minsw4(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_minsw4(vc, va, vb);
break;
case 0x3A:
/* MINUB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_minub8(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_minub8(vc, va, vb);
break;
case 0x3B:
/* MINUW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_minuw4(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_minuw4(vc, va, vb);
break;
case 0x3C:
/* MAXUB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_maxub8(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_maxub8(vc, va, vb);
break;
case 0x3D:
/* MAXUW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_maxuw4(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_maxuw4(vc, va, vb);
break;
case 0x3E:
/* MAXSB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_maxsb8(ra, rb, rc, islit, lit);
+ va = load_gpr(ctx, ra);
+ gen_helper_maxsb8(vc, va, vb);
break;
case 0x3F:
/* MAXSW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);
- gen_maxsw4(ra, rb, rc, islit, lit);
- break;
- case 0x70:
- /* FTOIT */
- REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
- REQUIRE_REG_31(rb);
- if (likely(rc != 31)) {
- if (ra != 31) {
- tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]);
- } else {
- tcg_gen_movi_i64(cpu_ir[rc], 0);
- }
- }
- break;
- case 0x78:
- /* FTOIS */
- REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
- REQUIRE_REG_31(rb);
- if (rc != 31) {
- TCGv_i32 tmp1 = tcg_temp_new_i32();
- if (ra != 31) {
- gen_helper_s_to_memory(tmp1, cpu_fir[ra]);
- } else {
- TCGv tmp2 = tcg_const_i64(0);
- gen_helper_s_to_memory(tmp1, tmp2);
- tcg_temp_free(tmp2);
- }
- tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1);
- tcg_temp_free_i32(tmp1);
- }
+ va = load_gpr(ctx, ra);
+ gen_helper_maxsw4(vc, va, vb);
break;
default:
goto invalid_opc;
}
break;
+
case 0x1D:
/* HW_MTPR (PALcode) */
#ifndef CONFIG_USER_ONLY
#else
goto invalid_opc;
#endif
+
case 0x1E:
/* HW_RET (PALcode) */
#ifndef CONFIG_USER_ONLY
/* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */
- TCGv tmp = tcg_temp_new();
+ tmp = tcg_temp_new();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
gen_helper_hw_ret(cpu_env, tmp);
tcg_temp_free(tmp);
} else {
- gen_helper_hw_ret(cpu_env, cpu_ir[rb]);
+ gen_helper_hw_ret(cpu_env, load_gpr(ctx, rb));
}
ret = EXIT_PC_UPDATED;
break;
#else
goto invalid_opc;
#endif
+
case 0x1F:
/* HW_ST (PALcode) */
#ifndef CONFIG_USER_ONLY
REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);
{
- TCGv addr, val;
- addr = tcg_temp_new();
- if (rb != 31) {
- tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
- } else {
- tcg_gen_movi_i64(addr, disp12);
- }
- if (ra != 31) {
- val = cpu_ir[ra];
- } else {
- val = tcg_temp_new();
- tcg_gen_movi_i64(val, 0);
- }
+ TCGv addr = tcg_temp_new();
+ va = load_gpr(ctx, ra);
+ vb = load_gpr(ctx, rb);
+
+ tcg_gen_addi_i64(addr, vb, disp12);
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access */
- gen_helper_stl_phys(cpu_env, addr, val);
+ gen_helper_stl_phys(cpu_env, addr, va);
break;
case 0x1:
/* Quadword physical access */
- gen_helper_stq_phys(cpu_env, addr, val);
+ gen_helper_stq_phys(cpu_env, addr, va);
break;
case 0x2:
/* Longword physical access with lock */
- gen_helper_stl_c_phys(val, cpu_env, addr, val);
+ gen_helper_stl_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va);
break;
case 0x3:
/* Quadword physical access with lock */
- gen_helper_stq_c_phys(val, cpu_env, addr, val);
+ gen_helper_stq_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va);
break;
case 0x4:
/* Longword virtual access */
/* Invalid */
goto invalid_opc;
}
- if (ra == 31) {
- tcg_temp_free(val);
- }
tcg_temp_free(addr);
break;
}
projects / qemu.git / blobdiff