* THE SOFTWARE.
*/
-#include "hw.h"
+#include "sysbus.h"
#include "scsi-disk.h"
#include "scsi.h"
*/
#ifdef DEBUG_ESP
-#define DPRINTF(fmt, args...) \
-do { printf("ESP: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) \
+ do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define DPRINTF(fmt, args...) do {} while (0)
+#define DPRINTF(fmt, ...) do {} while (0)
#endif
+#define ESP_ERROR(fmt, ...) \
+ do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
+
#define ESP_REGS 16
-#define TI_BUFSZ 32
+#define TI_BUFSZ 16
typedef struct ESPState ESPState;
struct ESPState {
+ SysBusDevice busdev;
uint32_t it_shift;
qemu_irq irq;
uint8_t rregs[ESP_REGS];
#define STAT_DI 0x01
#define STAT_CD 0x02
#define STAT_ST 0x03
-#define STAT_MI 0x06
-#define STAT_MO 0x07
+#define STAT_MO 0x06
+#define STAT_MI 0x07
#define STAT_PIO_MASK 0x06
#define STAT_TC 0x10
#define STAT_GE 0x40
#define STAT_INT 0x80
+#define BUSID_DID 0x07
+
#define INTR_FC 0x08
#define INTR_BS 0x10
#define INTR_DC 0x20
#define CFG1_RESREPT 0x40
-#define CFG2_MASK 0x15
-
#define TCHI_FAS100A 0x4
static void esp_raise_irq(ESPState *s)
uint32_t dmalen;
int target;
- dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
- target = s->wregs[ESP_WBUSID] & 7;
- DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
+ target = s->wregs[ESP_WBUSID] & BUSID_DID;
if (s->dma) {
+ dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
s->dma_memory_read(s->dma_opaque, buf, dmalen);
} else {
+ dmalen = s->ti_size;
+ memcpy(buf, s->ti_buf, dmalen);
buf[0] = 0;
- memcpy(&buf[1], s->ti_buf, dmalen);
- dmalen++;
}
+ DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
s->ti_size = 0;
s->ti_rptr = 0;
} else {
s->current_dev->read_data(s->current_dev, 0);
/* If there is still data to be read from the device then
- complete the DMA operation immeriately. Otherwise defer
+ complete the DMA operation immediately. Otherwise defer
until the scsi layer has completed. */
if (s->dma_left == 0 && s->ti_size > 0) {
esp_dma_done(s);
{
ESPState *s = opaque;
- esp_lower_irq(s);
-
memset(s->rregs, 0, ESP_REGS);
memset(s->wregs, 0, ESP_REGS);
s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
s->ti_wptr = 0;
s->dma = 0;
s->do_cmd = 0;
+
+ s->rregs[ESP_CFG1] = 7;
}
static void parent_esp_reset(void *opaque, int irq, int level)
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
- uint32_t saddr;
+ uint32_t saddr, old_val;
- saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
+ saddr = addr >> s->it_shift;
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
switch (saddr) {
case ESP_FIFO:
if (s->ti_size > 0) {
s->ti_size--;
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
- /* Data in/out. */
- fprintf(stderr, "esp: PIO data read not implemented\n");
+ /* Data out. */
+ ESP_ERROR("PIO data read not implemented\n");
s->rregs[ESP_FIFO] = 0;
} else {
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
}
break;
case ESP_RINTR:
- // Clear interrupt/error status bits
- s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE);
+ /* Clear sequence step, interrupt register and all status bits
+ except TC */
+ old_val = s->rregs[ESP_RINTR];
+ s->rregs[ESP_RINTR] = 0;
+ s->rregs[ESP_RSTAT] &= ~STAT_TC;
+ s->rregs[ESP_RSEQ] = SEQ_CD;
esp_lower_irq(s);
- break;
+
+ return old_val;
default:
break;
}
ESPState *s = opaque;
uint32_t saddr;
- saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
+ saddr = addr >> s->it_shift;
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
val);
switch (saddr) {
case ESP_FIFO:
if (s->do_cmd) {
s->cmdbuf[s->cmdlen++] = val & 0xff;
- } else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
- uint8_t buf;
- buf = val & 0xff;
- s->ti_size--;
- fprintf(stderr, "esp: PIO data write not implemented\n");
+ } else if (s->ti_size == TI_BUFSZ - 1) {
+ ESP_ERROR("fifo overrun\n");
} else {
s->ti_size++;
s->ti_buf[s->ti_wptr++] = val & 0xff;
case CMD_ICCS:
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
write_response(s);
+ s->rregs[ESP_RINTR] = INTR_FC;
+ s->rregs[ESP_RSTAT] |= STAT_MI;
break;
case CMD_MSGACC:
DPRINTF("Message Accepted (%2.2x)\n", val);
break;
case CMD_ENSEL:
DPRINTF("Enable selection (%2.2x)\n", val);
+ s->rregs[ESP_RINTR] = 0;
break;
default:
- DPRINTF("Unhandled ESP command (%2.2x)\n", val);
+ ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
break;
}
break;
break;
case ESP_WCCF ... ESP_WTEST:
break;
- case ESP_CFG2:
- s->rregs[saddr] = val & CFG2_MASK;
- break;
- case ESP_CFG3 ... ESP_RES4:
+ case ESP_CFG2 ... ESP_RES4:
s->rregs[saddr] = val;
break;
default:
- break;
+ ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
+ return;
}
s->wregs[saddr] = val;
}
qemu_put_buffer(f, s->rregs, ESP_REGS);
qemu_put_buffer(f, s->wregs, ESP_REGS);
- qemu_put_be32s(f, (uint32_t *)&s->ti_size);
+ qemu_put_sbe32s(f, &s->ti_size);
qemu_put_be32s(f, &s->ti_rptr);
qemu_put_be32s(f, &s->ti_wptr);
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
qemu_get_buffer(f, s->rregs, ESP_REGS);
qemu_get_buffer(f, s->wregs, ESP_REGS);
- qemu_get_be32s(f, (uint32_t *)&s->ti_size);
+ qemu_get_sbe32s(f, &s->ti_size);
qemu_get_be32s(f, &s->ti_rptr);
qemu_get_be32s(f, &s->ti_wptr);
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
return 0;
}
-void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
+static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id)
{
- ESPState *s = (ESPState *)opaque;
+ ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host));
if (id < 0) {
for (id = 0; id < ESP_MAX_DEVS; id++) {
+ if (id == (s->rregs[ESP_CFG1] & 0x7))
+ continue;
if (s->scsi_dev[id] == NULL)
break;
}
s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
}
-void *esp_init(target_phys_addr_t espaddr, int it_shift,
- espdma_memory_read_write dma_memory_read,
- espdma_memory_read_write dma_memory_write,
- void *dma_opaque, qemu_irq irq, qemu_irq *reset)
+void esp_init(target_phys_addr_t espaddr, int it_shift,
+ espdma_memory_read_write dma_memory_read,
+ espdma_memory_read_write dma_memory_write,
+ void *dma_opaque, qemu_irq irq, qemu_irq *reset)
{
- ESPState *s;
- int esp_io_memory;
+ DeviceState *dev;
+ SysBusDevice *s;
+ ESPState *esp;
+
+ dev = qdev_create(NULL, "esp");
+ esp = DO_UPCAST(ESPState, busdev.qdev, dev);
+ esp->dma_memory_read = dma_memory_read;
+ esp->dma_memory_write = dma_memory_write;
+ esp->dma_opaque = dma_opaque;
+ esp->it_shift = it_shift;
+ qdev_init(dev);
+ s = sysbus_from_qdev(dev);
+ sysbus_connect_irq(s, 0, irq);
+ sysbus_mmio_map(s, 0, espaddr);
+}
- s = qemu_mallocz(sizeof(ESPState));
- if (!s)
- return NULL;
+static void esp_init1(SysBusDevice *dev)
+{
+ ESPState *s = FROM_SYSBUS(ESPState, dev);
+ int esp_io_memory;
- s->irq = irq;
- s->it_shift = it_shift;
- s->dma_memory_read = dma_memory_read;
- s->dma_memory_write = dma_memory_write;
- s->dma_opaque = dma_opaque;
+ sysbus_init_irq(dev, &s->irq);
+ assert(s->it_shift != -1);
- esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
- cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory);
+ esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
+ sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
esp_reset(s);
- register_savevm("esp", espaddr, 3, esp_save, esp_load, s);
+ register_savevm("esp", -1, 3, esp_save, esp_load, s);
qemu_register_reset(esp_reset, s);
- *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
+ qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
+
+ scsi_bus_new(&dev->qdev, esp_scsi_attach);
+}
- return s;
+static void esp_register_devices(void)
+{
+ sysbus_register_dev("esp", sizeof(ESPState), esp_init1);
}
+
+device_init(esp_register_devices)
projects / qemu.git / blobdiff