* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#include "qemu/osdep.h"
-#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
#include "hw/sh4/sh.h"
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qemu/timer.h"
-
-//#define DEBUG_SERIAL
+#include "qemu/log.h"
+#include "trace.h"
#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE (1 << 1)
#define SH_RX_FIFO_LENGTH (16)
-typedef struct {
- MemoryRegion iomem;
- MemoryRegion iomem_p4;
- MemoryRegion iomem_a7;
+OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL)
+
+struct SHSerialState {
+ SysBusDevice parent;
uint8_t smr;
uint8_t brr;
uint8_t scr;
uint8_t rx_tail;
uint8_t rx_head;
- int freq;
- int feat;
+ uint8_t feat;
int flags;
int rtrg;
CharBackend chr;
- QEMUTimer *fifo_timeout_timer;
+ QEMUTimer fifo_timeout_timer;
uint64_t etu; /* Elementary Time Unit (ns) */
qemu_irq eri;
qemu_irq txi;
qemu_irq tei;
qemu_irq bri;
-} sh_serial_state;
+};
-static void sh_serial_clear_fifo(sh_serial_state * s)
+typedef struct {} SHSerialStateClass;
+
+OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE)
+
+static void sh_serial_clear_fifo(SHSerialState *s)
{
memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
s->rx_cnt = 0;
static void sh_serial_write(void *opaque, hwaddr offs,
uint64_t val, unsigned size)
{
- sh_serial_state *s = opaque;
+ SHSerialState *s = opaque;
+ DeviceState *d = DEVICE(s);
unsigned char ch;
-#ifdef DEBUG_SERIAL
- printf("sh_serial: write offs=0x%02x val=0x%02x\n",
- offs, val);
-#endif
- switch(offs) {
+ trace_sh_serial_write(d->id, size, offs, val);
+ switch (offs) {
case 0x00: /* SMR */
s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
return;
case 0x08: /* SCR */
/* TODO : For SH7751, SCIF mask should be 0xfb. */
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
- if (!(val & (1 << 5)))
+ if (!(val & (1 << 5))) {
s->flags |= SH_SERIAL_FLAG_TEND;
+ }
if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
qemu_set_irq(s->txi, val & (1 << 7));
}
case 0x0c: /* FTDR / TDR */
if (qemu_chr_fe_backend_connected(&s->chr)) {
ch = val;
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
+ /*
+ * XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks
+ */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->dr = val;
#endif
}
if (s->feat & SH_SERIAL_FEAT_SCIF) {
- switch(offs) {
+ switch (offs) {
case 0x10: /* FSR */
- if (!(val & (1 << 6)))
+ if (!(val & (1 << 6))) {
s->flags &= ~SH_SERIAL_FLAG_TEND;
- if (!(val & (1 << 5)))
+ }
+ if (!(val & (1 << 5))) {
s->flags &= ~SH_SERIAL_FLAG_TDE;
- if (!(val & (1 << 4)))
+ }
+ if (!(val & (1 << 4))) {
s->flags &= ~SH_SERIAL_FLAG_BRK;
- if (!(val & (1 << 1)))
+ }
+ if (!(val & (1 << 1))) {
s->flags &= ~SH_SERIAL_FLAG_RDF;
- if (!(val & (1 << 0)))
+ }
+ if (!(val & (1 << 0))) {
s->flags &= ~SH_SERIAL_FLAG_DR;
+ }
if (!(val & (1 << 1)) || !(val & (1 << 0))) {
if (s->rxi) {
case 0x24: /* LSR */
return;
}
- }
- else {
- switch(offs) {
+ } else {
+ switch (offs) {
#if 0
case 0x0c:
ret = s->dr;
return;
}
}
-
- fprintf(stderr, "sh_serial: unsupported write to 0x%02"
- HWADDR_PRIx "\n", offs);
- abort();
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: unsupported write to 0x%02" HWADDR_PRIx "\n",
+ __func__, offs);
}
static uint64_t sh_serial_read(void *opaque, hwaddr offs,
unsigned size)
{
- sh_serial_state *s = opaque;
- uint32_t ret = ~0;
+ SHSerialState *s = opaque;
+ DeviceState *d = DEVICE(s);
+ uint32_t ret = UINT32_MAX;
#if 0
- switch(offs) {
+ switch (offs) {
case 0x00:
ret = s->smr;
break;
}
#endif
if (s->feat & SH_SERIAL_FEAT_SCIF) {
- switch(offs) {
+ switch (offs) {
case 0x00: /* SMR */
ret = s->smr;
break;
break;
case 0x10: /* FSR */
ret = 0;
- if (s->flags & SH_SERIAL_FLAG_TEND)
+ if (s->flags & SH_SERIAL_FLAG_TEND) {
ret |= (1 << 6);
- if (s->flags & SH_SERIAL_FLAG_TDE)
+ }
+ if (s->flags & SH_SERIAL_FLAG_TDE) {
ret |= (1 << 5);
- if (s->flags & SH_SERIAL_FLAG_BRK)
+ }
+ if (s->flags & SH_SERIAL_FLAG_BRK) {
ret |= (1 << 4);
- if (s->flags & SH_SERIAL_FLAG_RDF)
+ }
+ if (s->flags & SH_SERIAL_FLAG_RDF) {
ret |= (1 << 1);
- if (s->flags & SH_SERIAL_FLAG_DR)
+ }
+ if (s->flags & SH_SERIAL_FLAG_DR) {
ret |= (1 << 0);
+ }
- if (s->scr & (1 << 5))
+ if (s->scr & (1 << 5)) {
s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
+ }
break;
case 0x14:
if (s->rx_cnt > 0) {
ret = s->rx_fifo[s->rx_tail++];
s->rx_cnt--;
- if (s->rx_tail == SH_RX_FIFO_LENGTH)
+ if (s->rx_tail == SH_RX_FIFO_LENGTH) {
s->rx_tail = 0;
- if (s->rx_cnt < s->rtrg)
+ }
+ if (s->rx_cnt < s->rtrg) {
s->flags &= ~SH_SERIAL_FLAG_RDF;
+ }
}
break;
case 0x18:
ret = 0;
break;
}
- }
- else {
- switch(offs) {
+ } else {
+ switch (offs) {
#if 0
case 0x0c:
ret = s->dr;
break;
}
}
-#ifdef DEBUG_SERIAL
- printf("sh_serial: read offs=0x%02x val=0x%x\n",
- offs, ret);
-#endif
+ trace_sh_serial_read(d->id, size, offs, ret);
- if (ret & ~((1 << 16) - 1)) {
- fprintf(stderr, "sh_serial: unsupported read from 0x%02"
- HWADDR_PRIx "\n", offs);
- abort();
+ if (ret > UINT16_MAX) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: unsupported read from 0x%02" HWADDR_PRIx "\n",
+ __func__, offs);
+ ret = 0;
}
return ret;
}
-static int sh_serial_can_receive(sh_serial_state *s)
+static int sh_serial_can_receive(SHSerialState *s)
{
return s->scr & (1 << 4);
}
-static void sh_serial_receive_break(sh_serial_state *s)
+static void sh_serial_receive_break(SHSerialState *s)
{
- if (s->feat & SH_SERIAL_FEAT_SCIF)
+ if (s->feat & SH_SERIAL_FEAT_SCIF) {
s->sr |= (1 << 4);
+ }
}
static int sh_serial_can_receive1(void *opaque)
{
- sh_serial_state *s = opaque;
+ SHSerialState *s = opaque;
return sh_serial_can_receive(s);
}
static void sh_serial_timeout_int(void *opaque)
{
- sh_serial_state *s = opaque;
+ SHSerialState *s = opaque;
s->flags |= SH_SERIAL_FLAG_RDF;
if (s->scr & (1 << 6) && s->rxi) {
static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
- sh_serial_state *s = opaque;
+ SHSerialState *s = opaque;
if (s->feat & SH_SERIAL_FEAT_SCIF) {
int i;
if (s->rx_cnt >= s->rtrg) {
s->flags |= SH_SERIAL_FLAG_RDF;
if (s->scr & (1 << 6) && s->rxi) {
- timer_del(s->fifo_timeout_timer);
+ timer_del(&s->fifo_timeout_timer);
qemu_set_irq(s->rxi, 1);
}
} else {
- timer_mod(s->fifo_timeout_timer,
+ timer_mod(&s->fifo_timeout_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
}
}
}
}
-static void sh_serial_event(void *opaque, int event)
+static void sh_serial_event(void *opaque, QEMUChrEvent event)
{
- sh_serial_state *s = opaque;
- if (event == CHR_EVENT_BREAK)
+ SHSerialState *s = opaque;
+ if (event == CHR_EVENT_BREAK) {
sh_serial_receive_break(s);
+ }
}
static const MemoryRegionOps sh_serial_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void sh_serial_init(MemoryRegion *sysmem,
- hwaddr base, int feat,
- uint32_t freq, Chardev *chr,
- qemu_irq eri_source,
- qemu_irq rxi_source,
- qemu_irq txi_source,
- qemu_irq tei_source,
- qemu_irq bri_source)
+static void sh_serial_reset(DeviceState *dev)
{
- sh_serial_state *s;
+ SHSerialState *s = SH_SERIAL(dev);
- s = g_malloc0(sizeof(sh_serial_state));
-
- s->feat = feat;
s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
s->rtrg = 1;
s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
s->sptr = 0;
- if (feat & SH_SERIAL_FEAT_SCIF) {
+ if (s->feat & SH_SERIAL_FEAT_SCIF) {
s->fcr = 0;
- }
- else {
+ } else {
s->dr = 0xff;
}
sh_serial_clear_fifo(s);
+}
- memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
- "serial", 0x100000000ULL);
-
- memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
- 0, 0x28);
- memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
-
- memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
- 0, 0x28);
- memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
-
- if (chr) {
- qemu_chr_fe_init(&s->chr, chr, &error_abort);
+static void sh_serial_realize(DeviceState *d, Error **errp)
+{
+ SHSerialState *s = SH_SERIAL(d);
+ MemoryRegion *iomem = g_malloc(sizeof(*iomem));
+
+ assert(d->id);
+ memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28);
+ sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem);
+ qdev_init_gpio_out_named(d, &s->eri, "eri", 1);
+ qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1);
+ qdev_init_gpio_out_named(d, &s->txi, "txi", 1);
+ qdev_init_gpio_out_named(d, &s->tei, "tei", 1);
+ qdev_init_gpio_out_named(d, &s->bri, "bri", 1);
+
+ if (qemu_chr_fe_backend_connected(&s->chr)) {
qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
sh_serial_receive1,
sh_serial_event, NULL, s, NULL, true);
}
- s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- sh_serial_timeout_int, s);
+ timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL,
+ sh_serial_timeout_int, s);
s->etu = NANOSECONDS_PER_SECOND / 9600;
- s->eri = eri_source;
- s->rxi = rxi_source;
- s->txi = txi_source;
- s->tei = tei_source;
- s->bri = bri_source;
+}
+
+static void sh_serial_finalize(Object *obj)
+{
+ SHSerialState *s = SH_SERIAL(obj);
+
+ timer_del(&s->fifo_timeout_timer);
+}
+
+static void sh_serial_init(Object *obj)
+{
+}
+
+static Property sh_serial_properties[] = {
+ DEFINE_PROP_CHR("chardev", SHSerialState, chr),
+ DEFINE_PROP_UINT8("features", SHSerialState, feat, 0),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void sh_serial_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ device_class_set_props(dc, sh_serial_properties);
+ dc->realize = sh_serial_realize;
+ dc->reset = sh_serial_reset;
+ /* Reason: part of SuperH CPU/SoC, needs to be wired up */
+ dc->user_creatable = false;
}
projects / qemu.git / blobdiff