* THE SOFTWARE.
*/
-#include "hw.h"
-#include "sun4m.h"
-#include "console.h"
#include "sysbus.h"
//#define DEBUG_IRQ
typedef struct SBIState {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t regs[SBI_NREGS];
uint32_t intreg_pending[MAX_CPUS];
qemu_irq cpu_irqs[MAX_CPUS];
{
}
-static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
+ unsigned size)
{
SBIState *s = opaque;
uint32_t saddr, ret;
return ret;
}
-static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void sbi_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned dize)
{
SBIState *s = opaque;
uint32_t saddr;
saddr = addr >> 2;
- DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
+ DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);
switch (saddr) {
default:
s->regs[saddr] = val;
}
}
-static CPUReadMemoryFunc * const sbi_mem_read[3] = {
- NULL,
- NULL,
- sbi_mem_readl,
+static const MemoryRegionOps sbi_mem_ops = {
+ .read = sbi_mem_read,
+ .write = sbi_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static CPUWriteMemoryFunc * const sbi_mem_write[3] = {
- NULL,
- NULL,
- sbi_mem_writel,
-};
-
-static void sbi_save(QEMUFile *f, void *opaque)
-{
- SBIState *s = opaque;
- unsigned int i;
-
- for (i = 0; i < MAX_CPUS; i++) {
- qemu_put_be32s(f, &s->intreg_pending[i]);
- }
-}
-
-static int sbi_load(QEMUFile *f, void *opaque, int version_id)
-{
- SBIState *s = opaque;
- unsigned int i;
-
- if (version_id != 1)
- return -EINVAL;
-
- for (i = 0; i < MAX_CPUS; i++) {
- qemu_get_be32s(f, &s->intreg_pending[i]);
+static const VMStateDescription vmstate_sbi = {
+ .name ="sbi",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
+ VMSTATE_END_OF_LIST()
}
+};
- return 0;
-}
-
-static void sbi_reset(void *opaque)
+static void sbi_reset(DeviceState *d)
{
- SBIState *s = opaque;
+ SBIState *s = container_of(d, SBIState, busdev.qdev);
unsigned int i;
for (i = 0; i < MAX_CPUS; i++) {
}
}
-static void sbi_init1(SysBusDevice *dev)
+static int sbi_init1(SysBusDevice *dev)
{
SBIState *s = FROM_SYSBUS(SBIState, dev);
- int sbi_io_memory;
unsigned int i;
qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
- sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
- sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory);
+ memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void sbi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- register_savevm("sbi", -1, 1, sbi_save, sbi_load, s);
- qemu_register_reset(sbi_reset, s);
- sbi_reset(s);
+ k->init = sbi_init1;
+ dc->reset = sbi_reset;
+ dc->vmsd = &vmstate_sbi;
}
-static SysBusDeviceInfo sbi_info = {
- .init = sbi_init1,
- .qdev.name = "sbi",
- .qdev.size = sizeof(SBIState),
+static TypeInfo sbi_info = {
+ .name = "sbi",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SBIState),
+ .class_init = sbi_class_init,
};
-static void sbi_register_devices(void)
+static void sbi_register_types(void)
{
- sysbus_register_withprop(&sbi_info);
+ type_register_static(&sbi_info);
}
-device_init(sbi_register_devices)
+type_init(sbi_register_types)