#include "flash.h"
#include "qemu-log.h"
#include "mips-bios.h"
-
-#define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff)
-
-#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
+#include "ide.h"
+#include "loader.h"
+#include "elf.h"
#define MAX_IDE_BUS 2
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };
-static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
-static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
-
static PITState *pit; /* PIT i8254 */
/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
static int mips_qemu_iomemtype = 0;
-static void load_kernel (CPUState *env)
+typedef struct ResetData {
+ CPUState *env;
+ uint64_t vector;
+} ResetData;
+
+static int64_t load_kernel(void)
{
- int64_t entry, kernel_low, kernel_high;
- long kernel_size, initrd_size;
+ int64_t entry, kernel_high;
+ long kernel_size, initrd_size, params_size;
ram_addr_t initrd_offset;
- int ret;
+ uint32_t *params_buf;
+ int big_endian;
- kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
- (uint64_t *)&entry, (uint64_t *)&kernel_low,
- (uint64_t *)&kernel_high);
+#ifdef TARGET_WORDS_BIGENDIAN
+ big_endian = 1;
+#else
+ big_endian = 0;
+#endif
+ kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
+ NULL, (uint64_t *)&entry, NULL,
+ (uint64_t *)&kernel_high, big_endian,
+ ELF_MACHINE, 1);
if (kernel_size >= 0) {
if ((entry & ~0x7fffffffULL) == 0x80000000)
entry = (int32_t)entry;
- env->active_tc.PC = entry;
} else {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
loaderparams.kernel_filename);
}
/* Store command line. */
+ params_size = 264;
+ params_buf = qemu_malloc(params_size);
+
+ params_buf[0] = tswap32(ram_size);
+ params_buf[1] = tswap32(0x12345678);
+
if (initrd_size > 0) {
- char buf[64];
- ret = snprintf(buf, 64, "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
- PHYS_TO_VIRT((uint32_t)initrd_offset),
- initrd_size);
- cpu_physical_memory_write((16 << 20) - 256, (void *)buf, 64);
+ snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s",
+ cpu_mips_phys_to_kseg0(NULL, initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline);
} else {
- ret = 0;
+ snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
}
- pstrcpy_targphys((16 << 20) - 256 + ret, 256,
- loaderparams.kernel_cmdline);
- stl_phys((16 << 20) - 260, 0x12345678);
- stl_phys((16 << 20) - 264, ram_size);
+ rom_add_blob_fixed("params", params_buf, params_size,
+ (16 << 20) - 264);
+
+ return entry;
}
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
- cpu_reset(env);
+ ResetData *s = (ResetData *)opaque;
+ CPUState *env = s->env;
- if (loaderparams.kernel_filename)
- load_kernel (env);
+ cpu_reset(env);
+ env->active_tc.PC = s->vector;
}
static const int sector_len = 32 * 1024;
ram_addr_t bios_offset;
int bios_size;
CPUState *env;
+ ResetData *reset_info;
RTCState *rtc_state;
int i;
qemu_irq *i8259;
- BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *dinfo;
/* init CPUs */
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- qemu_register_reset(main_cpu_reset, env);
+ reset_info = qemu_mallocz(sizeof(ResetData));
+ reset_info->env = env;
+ reset_info->vector = env->active_tc.PC;
+ qemu_register_reset(main_cpu_reset, reset_info);
/* allocate RAM */
if (ram_size > (256 << 20)) {
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
- load_kernel (env);
+ reset_info->vector = load_kernel();
}
/* Init CPU internal devices */
/* The PIC is attached to the MIPS CPU INT0 pin */
i8259 = i8259_init(env->irq[2]);
+ isa_bus_new(NULL);
+ isa_bus_irqs(i8259);
- rtc_state = rtc_init(0x70, i8259[8], 2000);
+ rtc_state = rtc_init(2000);
/* Register 64 KB of ISA IO space at 0x14000000 */
isa_mmio_init(0x14000000, 0x00010000);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
- serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
- serial_hds[i]);
+ serial_isa_init(i, serial_hds[i]);
}
}
isa_vga_init();
if (nd_table[0].vlan)
- isa_ne2000_init(0x300, i8259[9], &nd_table[0]);
+ isa_ne2000_init(0x300, 9, &nd_table[0]);
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
fprintf(stderr, "qemu: too many IDE bus\n");
}
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
- dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
- hd[i] = dinfo ? dinfo->bdrv : NULL;
+ hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
}
for(i = 0; i < MAX_IDE_BUS; i++)
- isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
+ isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[MAX_IDE_DEVS * i],
hd[MAX_IDE_DEVS * i + 1]);
- i8042_init(i8259[1], i8259[12], 0x60);
+ isa_create_simple("i8042");
}
static QEMUMachine mips_machine = {
projects / qemu.git / blobdiff