usb-ehci: frindex always is a 14 bits counter

[qemu.git] / hw / pflash_cfi02.c

diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index a97b9e6772dd9f7fed6557e745dfcc2af78d88db..3e2002e4b3662751a53e50cf7448ef216e274334 100644 (file)
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -39,6 +39,7 @@
 #include "flash.h"
 #include "qemu-timer.h"
 #include "block.h"
 #include "flash.h"
 #include "qemu-timer.h"
 #include "block.h"

+#include "exec-memory.h"

 
 //#define PFLASH_DEBUG
 #ifdef PFLASH_DEBUG
 
 //#define PFLASH_DEBUG
 #ifdef PFLASH_DEBUG


@@ -50,6 +51,8 @@ do {                                               \
 #define DPRINTF(fmt, ...) do { } while (0)
 #endif
 
 #define DPRINTF(fmt, ...) do { } while (0)
 #endif
 

+#define PFLASH_LAZY_ROMD_THRESHOLD 42
+

 struct pflash_t {
     BlockDriverState *bs;
     target_phys_addr_t base;
 struct pflash_t {
     BlockDriverState *bs;
     target_phys_addr_t base;


@@ -67,24 +70,39 @@ struct pflash_t {
     uint8_t cfi_len;
     uint8_t cfi_table[0x52];
     QEMUTimer *timer;
     uint8_t cfi_len;
     uint8_t cfi_table[0x52];
     QEMUTimer *timer;

-    ram_addr_t off;
-    int fl_mem;
+    /* The device replicates the flash memory across its memory space.  Emulate
+     * that by having a container (.mem) filled with an array of aliases
+     * (.mem_mappings) pointing to the flash memory (.orig_mem).
+     */
+    MemoryRegion mem;
+    MemoryRegion *mem_mappings;    /* array; one per mapping */
+    MemoryRegion orig_mem;

     int rom_mode;
     int rom_mode;

+    int read_counter; /* used for lazy switch-back to rom mode */

     void *storage;
 };
 
     void *storage;
 };
 

-static void pflash_register_memory(pflash_t *pfl, int rom_mode)
+/*
+ * Set up replicated mappings of the same region.
+ */
+static void pflash_setup_mappings(pflash_t *pfl)

 {
 {

-    unsigned long phys_offset = pfl->fl_mem;
-    int i;
+    unsigned i;
+    target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
+
+    memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
+    pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
+    for (i = 0; i < pfl->mappings; ++i) {
+        memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
+                                 &pfl->orig_mem, 0, size);
+        memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
+    }
+}

 
 

-    if (rom_mode)
-        phys_offset |= pfl->off | IO_MEM_ROMD;
+static void pflash_register_memory(pflash_t *pfl, int rom_mode)
+{
+    memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode);

     pfl->rom_mode = rom_mode;
     pfl->rom_mode = rom_mode;

-
-    for (i = 0; i < pfl->mappings; i++)
-        cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
-                                     pfl->chip_len, phys_offset);

 }
 
 static void pflash_timer (void *opaque)
 }
 
 static void pflash_timer (void *opaque)


@@ -103,18 +121,19 @@ static void pflash_timer (void *opaque)
     pfl->cmd = 0;
 }
 
     pfl->cmd = 0;
 }
 

-static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
+static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+                             int width, int be)

 {
 {

-    uint32_t boff;
+    target_phys_addr_t boff;

     uint32_t ret;
     uint8_t *p;
 
     uint32_t ret;
     uint8_t *p;
 

-    DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
+    DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);

     ret = -1;
     ret = -1;

-    if (pfl->rom_mode) {
-        /* Lazy reset of to ROMD mode */
-        if (pfl->wcycle == 0)
-            pflash_register_memory(pfl, 1);
+    /* Lazy reset to ROMD mode after a certain amount of read accesses */
+    if (!pfl->rom_mode && pfl->wcycle == 0 &&
+        ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
+        pflash_register_memory(pfl, 1);

     }
     offset &= pfl->chip_len - 1;
     boff = offset & 0xFF;
     }
     offset &= pfl->chip_len - 1;
     boff = offset & 0xFF;


@@ -140,27 +159,27 @@ static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
 //            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
             break;
         case 2:
 //            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
             break;
         case 2:

-#if defined(TARGET_WORDS_BIGENDIAN)
-            ret = p[offset] << 8;
-            ret |= p[offset + 1];
-#else
-            ret = p[offset];
-            ret |= p[offset + 1] << 8;
-#endif
+            if (be) {
+                ret = p[offset] << 8;
+                ret |= p[offset + 1];
+            } else {
+                ret = p[offset];
+                ret |= p[offset + 1] << 8;
+            }

 //            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
             break;
         case 4:
 //            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
             break;
         case 4:

-#if defined(TARGET_WORDS_BIGENDIAN)
-            ret = p[offset] << 24;
-            ret |= p[offset + 1] << 16;
-            ret |= p[offset + 2] << 8;
-            ret |= p[offset + 3];
-#else
-            ret = p[offset];
-            ret |= p[offset + 1] << 8;
-            ret |= p[offset + 2] << 16;
-            ret |= p[offset + 3] << 24;
-#endif
+            if (be) {
+                ret = p[offset] << 24;
+                ret |= p[offset + 1] << 16;
+                ret |= p[offset + 2] << 8;
+                ret |= p[offset + 3];
+            } else {
+                ret = p[offset];
+                ret |= p[offset + 1] << 8;
+                ret |= p[offset + 2] << 16;
+                ret |= p[offset + 3] << 24;
+            }

 //            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
             break;
         }
 //            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
             break;
         }


@@ -184,7 +203,7 @@ static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
         default:
             goto flash_read;
         }
         default:
             goto flash_read;
         }

-        DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
+        DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);

         break;
     case 0xA0:
     case 0x10:
         break;
     case 0xA0:
     case 0x10:


@@ -222,10 +241,10 @@ static void pflash_update(pflash_t *pfl, int offset,
     }
 }
 
     }
 }
 

-static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
-                          int width)
+static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
+                          uint32_t value, int width, int be)

 {
 {

-    uint32_t boff;
+    target_phys_addr_t boff;

     uint8_t *p;
     uint8_t cmd;
 
     uint8_t *p;
     uint8_t cmd;
 


@@ -237,11 +256,11 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
 #endif
         goto reset_flash;
     }
 #endif
         goto reset_flash;
     }

-    DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
+    DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,

             offset, value, width, pfl->wcycle);
     offset &= pfl->chip_len - 1;
 
             offset, value, width, pfl->wcycle);
     offset &= pfl->chip_len - 1;
 

-    DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
+    DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,

             offset, value, width);
     boff = offset & (pfl->sector_len - 1);
     if (pfl->width == 2)
             offset, value, width);
     boff = offset & (pfl->sector_len - 1);
     if (pfl->width == 2)


@@ -253,6 +272,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
         /* Set the device in I/O access mode if required */
         if (pfl->rom_mode)
             pflash_register_memory(pfl, 0);
         /* Set the device in I/O access mode if required */
         if (pfl->rom_mode)
             pflash_register_memory(pfl, 0);

+        pfl->read_counter = 0;

         /* We're in read mode */
     check_unlock0:
         if (boff == 0x55 && cmd == 0x98) {
         /* We're in read mode */
     check_unlock0:
         if (boff == 0x55 && cmd == 0x98) {


@@ -263,7 +283,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
             return;
         }
         if (boff != pfl->unlock_addr[0] || cmd != 0xAA) {
             return;
         }
         if (boff != pfl->unlock_addr[0] || cmd != 0xAA) {

-            DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
+            DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",

                     __func__, boff, cmd, pfl->unlock_addr[0]);
             goto reset_flash;
         }
                     __func__, boff, cmd, pfl->unlock_addr[0]);
             goto reset_flash;
         }


@@ -273,7 +293,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
         /* We started an unlock sequence */
     check_unlock1:
         if (boff != pfl->unlock_addr[1] || cmd != 0x55) {
         /* We started an unlock sequence */
     check_unlock1:
         if (boff != pfl->unlock_addr[1] || cmd != 0x55) {

-            DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
+            DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,

                     boff, cmd);
             goto reset_flash;
         }
                     boff, cmd);
             goto reset_flash;
         }


@@ -282,7 +302,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
     case 2:
         /* We finished an unlock sequence */
         if (!pfl->bypass && boff != pfl->unlock_addr[0]) {
     case 2:
         /* We finished an unlock sequence */
         if (!pfl->bypass && boff != pfl->unlock_addr[0]) {

-            DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
+            DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,

                     boff, cmd);
             goto reset_flash;
         }
                     boff, cmd);
             goto reset_flash;
         }


@@ -307,38 +327,40 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
             /* We need another unlock sequence */
             goto check_unlock0;
         case 0xA0:
             /* We need another unlock sequence */
             goto check_unlock0;
         case 0xA0:

-            DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
+            DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",

                     __func__, offset, value, width);
             p = pfl->storage;
                     __func__, offset, value, width);
             p = pfl->storage;

-            switch (width) {
-            case 1:
-                p[offset] &= value;
-                pflash_update(pfl, offset, 1);
-                break;
-            case 2:
-#if defined(TARGET_WORDS_BIGENDIAN)
-                p[offset] &= value >> 8;
-                p[offset + 1] &= value;
-#else
-                p[offset] &= value;
-                p[offset + 1] &= value >> 8;
-#endif
-                pflash_update(pfl, offset, 2);
-                break;
-            case 4:
-#if defined(TARGET_WORDS_BIGENDIAN)
-                p[offset] &= value >> 24;
-                p[offset + 1] &= value >> 16;
-                p[offset + 2] &= value >> 8;
-                p[offset + 3] &= value;
-#else
-                p[offset] &= value;
-                p[offset + 1] &= value >> 8;
-                p[offset + 2] &= value >> 16;
-                p[offset + 3] &= value >> 24;
-#endif
-                pflash_update(pfl, offset, 4);
-                break;
+            if (!pfl->ro) {
+                switch (width) {
+                case 1:
+                    p[offset] &= value;
+                    pflash_update(pfl, offset, 1);
+                    break;
+                case 2:
+                    if (be) {
+                        p[offset] &= value >> 8;
+                        p[offset + 1] &= value;
+                    } else {
+                        p[offset] &= value;
+                        p[offset + 1] &= value >> 8;
+                    }
+                    pflash_update(pfl, offset, 2);
+                    break;
+                case 4:
+                    if (be) {
+                        p[offset] &= value >> 24;
+                        p[offset + 1] &= value >> 16;
+                        p[offset + 2] &= value >> 8;
+                        p[offset + 3] &= value;
+                    } else {
+                        p[offset] &= value;
+                        p[offset + 1] &= value >> 8;
+                        p[offset + 2] &= value >> 16;
+                        p[offset + 3] &= value >> 24;
+                    }
+                    pflash_update(pfl, offset, 4);
+                    break;
+                }

             }
             pfl->status = 0x00 | ~(value & 0x80);
             /* Let's pretend write is immediate */
             }
             pfl->status = 0x00 | ~(value & 0x80);
             /* Let's pretend write is immediate */


@@ -362,7 +384,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
     case 4:
         switch (pfl->cmd) {
         case 0xA0:
     case 4:
         switch (pfl->cmd) {
         case 0xA0:

-            /* Ignore writes while flash data write is occuring */
+            /* Ignore writes while flash data write is occurring */

             /* As we suppose write is immediate, this should never happen */
             return;
         case 0x80:
             /* As we suppose write is immediate, this should never happen */
             return;
         case 0x80:


@@ -378,31 +400,35 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
         switch (cmd) {
         case 0x10:
             if (boff != pfl->unlock_addr[0]) {
         switch (cmd) {
         case 0x10:
             if (boff != pfl->unlock_addr[0]) {

-                DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
+                DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",

                         __func__, offset);
                 goto reset_flash;
             }
             /* Chip erase */
             DPRINTF("%s: start chip erase\n", __func__);
                         __func__, offset);
                 goto reset_flash;
             }
             /* Chip erase */
             DPRINTF("%s: start chip erase\n", __func__);

-            memset(pfl->storage, 0xFF, pfl->chip_len);
+            if (!pfl->ro) {
+                memset(pfl->storage, 0xFF, pfl->chip_len);
+                pflash_update(pfl, 0, pfl->chip_len);
+            }

             pfl->status = 0x00;
             pfl->status = 0x00;

-            pflash_update(pfl, 0, pfl->chip_len);

             /* Let's wait 5 seconds before chip erase is done */
             qemu_mod_timer(pfl->timer,
             /* Let's wait 5 seconds before chip erase is done */
             qemu_mod_timer(pfl->timer,

-                           qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
+                           qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));

             break;
         case 0x30:
             /* Sector erase */
             p = pfl->storage;
             offset &= ~(pfl->sector_len - 1);
             break;
         case 0x30:
             /* Sector erase */
             p = pfl->storage;
             offset &= ~(pfl->sector_len - 1);

-            DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
+            DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,

                     offset);
                     offset);

-            memset(p + offset, 0xFF, pfl->sector_len);
-            pflash_update(pfl, offset, pfl->sector_len);
+            if (!pfl->ro) {
+                memset(p + offset, 0xFF, pfl->sector_len);
+                pflash_update(pfl, offset, pfl->sector_len);
+            }

             pfl->status = 0x00;
             /* Let's wait 1/2 second before sector erase is done */
             qemu_mod_timer(pfl->timer,
             pfl->status = 0x00;
             /* Let's wait 1/2 second before sector erase is done */
             qemu_mod_timer(pfl->timer,

-                           qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
+                           qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));

             break;
         default:
             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
             break;
         default:
             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);


@@ -451,57 +477,102 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
 }
 
 
 }
 
 

-static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+{
+    return pflash_read(opaque, addr, 1, 1);
+}
+
+static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+{
+    return pflash_read(opaque, addr, 1, 0);
+}
+
+static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+{
+    pflash_t *pfl = opaque;
+
+    return pflash_read(pfl, addr, 2, 1);
+}
+
+static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)

 {
 {

-    return pflash_read(opaque, addr, 1);
+    pflash_t *pfl = opaque;
+
+    return pflash_read(pfl, addr, 2, 0);

 }
 
 }
 

-static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)

 {
     pflash_t *pfl = opaque;
 
 {
     pflash_t *pfl = opaque;
 

-    return pflash_read(pfl, addr, 2);
+    return pflash_read(pfl, addr, 4, 1);

 }
 
 }
 

-static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)

 {
     pflash_t *pfl = opaque;
 
 {
     pflash_t *pfl = opaque;
 

-    return pflash_read(pfl, addr, 4);
+    return pflash_read(pfl, addr, 4, 0);
+}
+
+static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+                             uint32_t value)
+{
+    pflash_write(opaque, addr, value, 1, 1);
+}
+
+static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+                             uint32_t value)
+{
+    pflash_write(opaque, addr, value, 1, 0);

 }
 
 }
 

-static void pflash_writeb (void *opaque, target_phys_addr_t addr,
-                           uint32_t value)
+static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+                             uint32_t value)

 {
 {

-    pflash_write(opaque, addr, value, 1);
+    pflash_t *pfl = opaque;
+
+    pflash_write(pfl, addr, value, 2, 1);

 }
 
 }
 

-static void pflash_writew (void *opaque, target_phys_addr_t addr,
-                           uint32_t value)
+static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+                             uint32_t value)

 {
     pflash_t *pfl = opaque;
 
 {
     pflash_t *pfl = opaque;
 

-    pflash_write(pfl, addr, value, 2);
+    pflash_write(pfl, addr, value, 2, 0);

 }
 
 }
 

-static void pflash_writel (void *opaque, target_phys_addr_t addr,
-                           uint32_t value)
+static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+                             uint32_t value)

 {
     pflash_t *pfl = opaque;
 
 {
     pflash_t *pfl = opaque;
 

-    pflash_write(pfl, addr, value, 4);
+    pflash_write(pfl, addr, value, 4, 1);

 }
 
 }
 

-static CPUWriteMemoryFunc * const pflash_write_ops[] = {
-    &pflash_writeb,
-    &pflash_writew,
-    &pflash_writel,
+static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+                             uint32_t value)
+{
+    pflash_t *pfl = opaque;
+
+    pflash_write(pfl, addr, value, 4, 0);
+}
+
+static const MemoryRegionOps pflash_cfi02_ops_be = {
+    .old_mmio = {
+        .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
+        .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
+    },
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 };
 

-static CPUReadMemoryFunc * const pflash_read_ops[] = {
-    &pflash_readb,
-    &pflash_readw,
-    &pflash_readl,
+static const MemoryRegionOps pflash_cfi02_ops_le = {
+    .old_mmio = {
+        .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
+        .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
+    },
+    .endianness = DEVICE_NATIVE_ENDIAN,

 };
 
 /* Count trailing zeroes of a 32 bits quantity */
 };
 
 /* Count trailing zeroes of a 32 bits quantity */


@@ -528,7 +599,9 @@ static int ctz32 (uint32_t n)
     }
     if (!(n & 0x1)) {
         ret++;
     }
     if (!(n & 0x1)) {
         ret++;

+#if 0 /* This is not necessary as n is never 0 */

         n = n >> 1;
         n = n >> 1;

+#endif

     }
 #if 0 /* This is not necessary as n is never 0 */
     if (!n)
     }
 #if 0 /* This is not necessary as n is never 0 */
     if (!n)


@@ -538,15 +611,19 @@ static int ctz32 (uint32_t n)
     return ret;
 }
 
     return ret;
 }
 

-pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
+pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+                                DeviceState *qdev, const char *name,
+                                target_phys_addr_t size,

                                 BlockDriverState *bs, uint32_t sector_len,
                                 int nb_blocs, int nb_mappings, int width,
                                 uint16_t id0, uint16_t id1,
                                 uint16_t id2, uint16_t id3,
                                 BlockDriverState *bs, uint32_t sector_len,
                                 int nb_blocs, int nb_mappings, int width,
                                 uint16_t id0, uint16_t id1,
                                 uint16_t id2, uint16_t id3,

-                                uint16_t unlock_addr0, uint16_t unlock_addr1)
+                                uint16_t unlock_addr0, uint16_t unlock_addr1,
+                                int be)

 {
     pflash_t *pfl;
     int32_t chip_len;
 {
     pflash_t *pfl;
     int32_t chip_len;

+    int ret;

 
     chip_len = sector_len * nb_blocs;
     /* XXX: to be fixed */
 
     chip_len = sector_len * nb_blocs;
     /* XXX: to be fixed */


@@ -555,29 +632,37 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
         return NULL;
 #endif
         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
         return NULL;
 #endif

-    pfl = qemu_mallocz(sizeof(pflash_t));
-    /* FIXME: Allocate ram ourselves.  */
-    pfl->storage = qemu_get_ram_ptr(off);
-    pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops,
-                                         pfl);
-    pfl->off = off;
+    pfl = g_malloc0(sizeof(pflash_t));
+    memory_region_init_rom_device(
+        &pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl,
+        name, size);
+    vmstate_register_ram(&pfl->orig_mem, qdev);
+    pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);

     pfl->base = base;
     pfl->chip_len = chip_len;
     pfl->mappings = nb_mappings;
     pfl->base = base;
     pfl->chip_len = chip_len;
     pfl->mappings = nb_mappings;

-    pflash_register_memory(pfl, 1);

     pfl->bs = bs;
     if (pfl->bs) {
         /* read the initial flash content */
     pfl->bs = bs;
     if (pfl->bs) {
         /* read the initial flash content */

-        bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
+        ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
+        if (ret < 0) {
+            g_free(pfl);
+            return NULL;
+        }
+        bdrv_attach_dev_nofail(pfl->bs, pfl);

     }
     }

-#if 0 /* XXX: there should be a bit to set up read-only,
-       *      the same way the hardware does (with WP pin).
-       */
-    pfl->ro = 1;
-#else
-    pfl->ro = 0;
-#endif
-    pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
+
+    pflash_setup_mappings(pfl);
+    pfl->rom_mode = 1;
+    memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
+
+    if (pfl->bs) {
+        pfl->ro = bdrv_is_read_only(pfl->bs);
+    } else {
+        pfl->ro = 0;
+    }
+
+    pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);

     pfl->sector_len = sector_len;
     pfl->width = width;
     pfl->wcycle = 0;
     pfl->sector_len = sector_len;
     pfl->width = width;
     pfl->wcycle = 0;